FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-02-06 08:38:23 +08:00
Code Issues Projects Releases Wiki Activity
543 Commits 1 Branch 0 Tags
Commit Graph

124 Commits

Author SHA1 Message Date
Alex Forencich
c6c83a7c68 Remove recursively-expanded macros for module parameters in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 15:58:34 -08:00
Alex Forencich
9c5c6e6edf Rework parameter handling in example design makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-29 22:56:53 -08:00
Alex Forencich
91450fcab7 PCIe flow control is handled in shim; remove flow control from PCIe DMA interface 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 13:47:02 -07:00
Alex Forencich
3f3be1e14d Implement flow control for P-Tile 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-02 22:57:27 -07:00
Alex Forencich
7f0bd00170 Implement flow control for Stratix 10 shim 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-01 13:19:01 -07:00
Alex Forencich
9c434687a8 Add flow control credit counter to TLP FIFO MUX module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-31 17:35:07 -07:00
Alex Forencich
b1b82a3f2b Add pause inputs to TLP mux modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-29 17:16:05 -07:00
Alex Forencich
0d9b1d0fb0 Implement flow control in UltraScale shim 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-26 14:01:00 -07:00
Alex Forencich
a5fe40cd42 Fix JTAG index 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-22 22:34:26 -07:00
Alex Forencich
a53509de68 Add instance names 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-22 22:34:04 -07:00
Alex Forencich
90c65dfed7 Fix PBA offsets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-22 22:33:38 -07:00
Alex Forencich
5fe904545c Testbench cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-13 16:35:51 -07:00
Alex Forencich
fc90d7f44d Strip version number 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-13 00:40:43 -07:00
Alex Forencich
dbcd211ce1 Add example design for DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-13 00:31:59 -07:00
Alex Forencich
c5382f5e7f Add example design for Stratix 10 DX dev kit 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-13 00:31:39 -07:00
Alex Forencich
cf3029364d Add P-Tile example design core module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-13 00:31:13 -07:00
Alex Forencich
3f334dbbbb Use MSI-X in example designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-12 23:32:51 -07:00
Alex Forencich
e2588cd995 Clean up TCL scripts 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-12 16:23:54 -07:00
Alex Forencich
a17c33e3c6 Update example designs to enable TLP straddling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-04 01:31:15 -07:00
Alex Forencich
19b1af0388 Update Xilinx UltraScale shims to support TLP straddling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-04 00:46:07 -07:00
Alex Forencich
a44f9852c2 Update Stratix 10 H-tile/L-tile shim to support segments 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 23:48:46 -07:00
Alex Forencich
26c7128b7e Tie off unused port 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 23:42:03 -07:00
Alex Forencich
cc1278f9d9 Update PCIe TLP mux to handle multiple segments 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 23:40:35 -07:00
Alex Forencich
23705eb873 Update PCIe TLP demux to handle segments 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 23:39:38 -07:00
Alex Forencich
87e155949c Add a simple block transfer measurement 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-19 22:52:16 -07:00
Alex Forencich
48daa02897 Update example designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-07 14:35:39 -07:00
Alex Forencich
df32016724 Add sequence number ports to TLP mux and demux modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 17:34:12 -07:00
Alex Forencich
70dc92c24e Rework TLP interface parametrization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 13:27:04 -07:00
Alex Forencich
ee59fc10e0 Update testbenches for new version of cocotbext-pcie 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 13:26:27 -07:00
Alex Forencich
228d20b3f4 Update example designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-02 23:36:01 -07:00
Alex Forencich
ba5188dd93 Update testbenches for new version of cocotbext-pcie 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-02 23:33:52 -07:00
Alex Forencich
0b815522b0 Sync example design testbenches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-20 00:43:55 -07:00
Alex Forencich
e4b1df0ddb Fix immediate enable register implementation in example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-20 00:43:21 -07:00
Alex Forencich
32b4f2cb1f Improve block operation tests 2022-04-04 15:21:25 -07:00
Alex Forencich
e7a83364d0 Update testbenches 2022-04-04 15:05:21 -07:00
Alex Forencich
389911e126 Update example design to test immediate write 2022-04-04 15:04:57 -07:00
Alex Forencich
32fe17ad91 Return 0 for unmatched registers 2022-03-25 23:56:42 -07:00
Alex Forencich
c62df81292 Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH 2022-02-15 00:39:46 -08:00
Alex Forencich
74e4322d43 Fix bug in example design core logic 2022-01-17 21:45:49 -08:00
Alex Forencich
bac4e4066f Use start_soon instead of fork 2021-12-10 17:44:37 -08:00
Alex Forencich
d1210d02a3 Add example design for ZCU106 2021-11-18 16:33:39 -08:00
Alex Forencich
0830ca6a7a Add example design for VCU1525 2021-11-18 16:32:38 -08:00
Alex Forencich
fb4b32fba0 Add example design for VCU118 2021-11-18 16:31:55 -08:00
Alex Forencich
cef69d1e1f Add example design for VCU108 2021-11-18 16:31:18 -08:00
Alex Forencich
6740ddafaf Add example design for ExaNIC X25 2021-11-18 16:29:52 -08:00
Alex Forencich
0cbe4897da Add example design for Alveo U50 2021-11-18 16:28:39 -08:00
Alex Forencich
068ea6edc2 Add example design for Alveo U280 2021-11-18 16:27:48 -08:00
Alex Forencich
12fea955d2 Add example design for Alveo U250 2021-11-18 16:26:43 -08:00
Alex Forencich
6e5f9f33f2 Add example design for Alveo U200 2021-11-18 16:25:59 -08:00
Alex Forencich
057edebc36 Add example design for ADM-PCIE-9V3 2021-11-18 16:21:28 -08:00