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Author SHA1 Message Date
Alex Forencich
587b4d5743 fpga/mqnic/DK_DEV_1SDX_P_A: Add 100G mqnic design for DK-DEV-1SDX-P-A 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-22 22:07:32 -07:00
Alex Forencich
3d8bbc4b1c modules/mqnic: Add I2C code for Intel dev kits 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-22 21:58:56 -07:00
Alex Forencich
d1546c0f8e modules/mqnic: Update device IDs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-22 21:56:08 -07:00
Alex Forencich
0634b86539 fpga/mqnic/DK_DEV_1SDX_P_A: Implement I2C interface on DK-DEV-1SDX-P-A 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-22 20:24:50 -07:00
Alex Forencich
52068fbb31 fpga/mqnic: Rename Intel development kit designs based on part number 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-20 21:51:35 -07:00
Alex Forencich
56df4cb677 lib/mqnic: Add more JTAG IDs for Xilinx devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-16 23:14:23 -07:00
Alex Forencich
3c33590ca7 Update device lists 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-16 01:12:31 -07:00
Alex Forencich
526bcdb7b1 fpga/mqnic/DK_DEV_AGF014EA: Add 25G mqnic design for DK-DEV-AGF014EA 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-16 01:11:11 -07:00
Alex Forencich
19cbfeccaa fpga/mqnic/DK_DEV_AGF014EA: Add 100G mqnic design for DK-DEV-AGF014EA 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-16 01:10:43 -07:00
Alex Forencich
f4c016a46c fpga/mqnic/DE10-Agilex: Drop part suffix for production parts 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-15 16:56:10 -07:00
Alex Forencich
14be62110e fpga/mqnic: Write compressed SOF files 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-15 16:29:37 -07:00
Alex Forencich
adeb6d7a11 fpga/mqnic/DE10_Agilex: Report correct FPGA IDs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-15 16:26:39 -07:00
Alex Forencich
a3319d50b6 fpga/mqnic: Implement workaround for Quartus MLAB RAM read enable bug 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-14 01:21:36 -07:00
Alex Forencich
95af2136b1 fpga/common: Increase event FIFO size 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-14 01:03:19 -07:00
Alex Forencich
bb158d568f Add RX indirection table 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-10 15:05:32 -07:00
Alex Forencich
30379cd8a3 Add phase tag to events and completions to avoid queue pointer reads 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-06 20:43:13 -07:00
Alex Forencich
54b3c8199c fpga/common: Add re-arm bit in tail pointer register in completion queue manager 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-06 16:58:50 -07:00
Alex Forencich
04ede2e535 fpga/common: Update port timing constraints to not mark ASYNC_REG on the first flip flop in the status sync chains for better placement flexibility 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-06 14:34:22 -07:00
Alex Forencich
c273b7f4ad mqnic: Register MIG resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-05 17:06:57 -07:00
Alex Forencich
394dc2d723 fpga/common: Add phase bit to queue managers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-05 01:38:46 -07:00
Alex Forencich
a8feaf2383 Advance TX/RX queue pointers based on completion records instead of MMIO reads 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-04 22:12:32 -07:00
Alex Forencich
147f09e62e scripts: Dump registers before and after running tests 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-04 18:24:27 -07:00
Alex Forencich
1a8adb646f modules/mqnic: Add ifdefs for kernel API changes related to netif_napi_add/netif_tx_napi_add 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-04 01:15:50 -07:00
Alex Forencich
d06fbaf178 fpga/common/tb: Rework driver model to better match C code 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-31 17:44:06 -07:00
Alex Forencich
ec1d7fe904 fpga/common/tb: Remove old interrupt handler 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-31 16:58:53 -07:00
Alex Forencich
f54fe4100a fpga/mqnic: Update Intel IP TCL files for E-Tile 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-30 13:50:59 -07:00
Alex Forencich
047b1a4cec merged changes in axi 2023-03-30 00:13:02 -07:00
Alex Forencich
38915fb533 Fix reset CDC in AXI VFIFO 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-30 00:12:13 -07:00
Alex Forencich
dd07e65330 fpga/mqnic/XUPP3R: Fix placement constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-30 00:10:59 -07:00
Alex Forencich
3d06b34679 fpga: Add DRAM bandwidth test to DMA benchmark application 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-29 14:27:46 -07:00
Alex Forencich
d6bac395f3 fpga/app/dma_bench: Add DRAM test channel module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-29 14:23:52 -07:00
Alex Forencich
4245317b15 merged changes in axi 2023-03-28 22:01:15 -07:00
Alex Forencich
59d37ee850 Add AXI virtual FIFO 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-28 20:59:47 -07:00
Alex Forencich
99ff2e81b7 Update cocotbext-axi version 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-28 19:15:40 -07:00
Alex Forencich
223c6c020d fpga/common: Add DRAM/HBM to core testbenches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-27 18:12:50 -07:00
Alex Forencich
b9945d3986 fpga/common: Pull out core_inst to simplify setup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-26 23:18:55 -07:00
Alex Forencich
efd6989795 Update cocotbext-axi version 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-24 11:12:17 -07:00
Alex Forencich
7c6c39e446 fpga/mqnic: Move implementation strategy setting into config.tcl 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-24 00:40:12 -07:00
Alex Forencich
554369b33b fpga/mqnic: Update makefile path handling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-24 00:39:45 -07:00
Alex Forencich
853dca8c4c fpga/mqnic: Always create SLR pblocks 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-24 00:39:18 -07:00
Alex Forencich
ca07a23afc fpga/common: Add extra non-ASYNC_REG registers on transceiver resets to permit replication 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-24 21:34:42 -08:00
Alex Forencich
0f86ea9bb1 fpga/common: Remove unnecessary reset from clock info register block 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-24 21:32:30 -08:00
Alex Forencich
77adf30dad Add missing serdes_rx_reset_req output to 10G MAC+PHY modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-22 17:36:01 -08:00
Alex Forencich
1682389fd0 Remove recursively-expanded macros for module parameters in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 16:24:52 -08:00
Alex Forencich
5d298e8465 Update ubuntu version in CI 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 16:20:22 -08:00
Alex Forencich
24c74b3003 merged changes in pcie 2023-02-17 16:20:00 -08:00
Alex Forencich
e7953da0c0 merged changes in eth 2023-02-17 16:19:50 -08:00
Alex Forencich
93ceea327e merged changes in axi 2023-02-17 16:19:45 -08:00
Alex Forencich
00c200f881 Remove recursively-expanded macros for module parameters in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 16:18:44 -08:00
Alex Forencich
1ad973f7a7 Update ubuntu version in CI 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 16:05:56 -08:00