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12 Commits

Author SHA1 Message Date
Alex Forencich
217217b45e Remove unused table fields 2019-12-30 22:02:22 -08:00
Alex Forencich
db9e1df1fa Update pipelining to enable URAM inference 2019-12-28 01:13:57 -08:00
Alex Forencich
45a33b8293 Fix scheduler bug 2019-12-16 14:13:01 -08:00
Alex Forencich
4dafedca27 Reschedule queue if necessary 2019-12-06 14:21:20 -08:00
Alex Forencich
f65b139797 Add scheduler control input to tx_scheduler_rr 2019-11-05 16:56:10 -08:00
Alex Forencich
8fa7e40507 Use new DMA subsystem 2019-10-17 16:02:14 -07:00
Alex Forencich
2e27d6ae2f Improve tx_scheduler_rr timing 2019-09-14 23:32:34 -07:00
Alex Forencich
5048864d86 Update tx_scheduler to handle out of order operations 2019-09-02 09:02:53 -07:00
Alex Forencich
c9a17cdf90 Init scheduler queue state on reset 2019-08-13 13:51:50 -07:00
Alex Forencich
94c8dabad6 Rewrite scheduler 2019-08-13 00:45:01 -07:00
Alex Forencich
26f6774182 Parameter updates and documentation 2019-07-27 23:47:46 -07:00
Alex Forencich
12f215fe26 Add round robin transmit scheduler 2019-07-17 16:40:35 -07:00