341 Commits

Author	SHA1	Message	Date
Alex Forencich	4ed99c6f87	Remove CMS IP version number	2021-07-03 00:09:10 -07:00
Alex Forencich	c926fd2ca1	Remove extraneous imports	2021-06-28 22:35:22 -07:00
minseongg	9af504a6c0	Update cmac_pad testbench	2021-06-28 22:33:57 -07:00
minseongg	8db2faddc6	Update cmac_pad testbench	2021-06-28 22:33:57 -07:00
minseongg	dc5c8232f9	Add cmac_pad testbench	2021-06-28 22:33:57 -07:00
Alex Forencich	b1c6bdbd88	merged changes in pcie	2021-06-27 14:05:12 -07:00
Alex Forencich	0a7f1ccbbe	Remove string parameters	2021-06-02 18:18:23 -07:00
Alex Forencich	4d89e70b92	merged changes in axi	2021-06-02 17:57:51 -07:00
Alex Forencich	bea7ff909f	merged changes in pcie	2021-06-02 17:57:45 -07:00
Alex Forencich	7558949e12	merged changes in eth	2021-06-02 17:57:39 -07:00
Alex Forencich	15cb21dbd1	Reorganize timing constraints	2021-05-20 15:24:01 -07:00
Alex Forencich	5ebc741ffe	merged changes in axi	2021-05-20 15:17:25 -07:00
Alex Forencich	955fdbf391	merged changes in pcie	2021-05-20 15:17:19 -07:00
Alex Forencich	892aa58004	merged changes in eth	2021-05-20 15:13:16 -07:00
Alex Forencich	7b2a0a1aed	Update testbenches	2021-04-28 20:54:44 -07:00
Alex Forencich	0916fb6686	Enable PTP on NetFPGA SUME	2021-04-01 21:58:32 -07:00
Alex Forencich	1bb5d8ab56	Add PTP support at 100G on VCU118	2021-04-01 18:02:58 -07:00
Alex Forencich	cf6e8bba99	Add PTP support at 100G on ADM-PCIE-9V3	2021-04-01 18:02:26 -07:00
Alex Forencich	d4b009b6d2	Add PTP support at 100G on VCU1525	2021-04-01 17:25:57 -07:00
Alex Forencich	2d20ee2807	Add PTP support at 100G on Alveo U50	2021-04-01 17:08:06 -07:00
Alex Forencich	275c0e98e9	Add PTP support at 100G on Alveo U250	2021-04-01 16:53:00 -07:00
Alex Forencich	77bb4b9dd8	Add PTP support at 100G on Alveo U200	2021-04-01 16:52:00 -07:00
Alex Forencich	2975e075d4	Add PTP support at 100G on Alveo U280	2021-04-01 16:31:23 -07:00
Alex Forencich	31c902685a	Add PTP support at 100G on fb2CG@KU15P	2021-04-01 16:29:52 -07:00
Alex Forencich	8b70695fa0	merged changes in eth	2021-03-30 22:25:28 -07:00
Alex Forencich	5d6723cc69	merged changes in pcie	2021-03-30 21:54:12 -07:00
Alex Forencich	c7896bef92	Use correct assignment type	2021-03-30 21:50:25 -07:00
Alex Forencich	2afbd1f15b	Enable PTP in 25G designs	2021-03-30 18:53:52 -07:00
Alex Forencich	1aeeb0bbe2	Update designs for PTP CDC and Ethernet MAC module changes	2021-03-30 16:41:31 -07:00
Alex Forencich	1c9430823b	merged changes in pcie	2021-03-30 16:20:33 -07:00
Alex Forencich	7993bc0125	merged changes in axi	2021-03-30 16:20:28 -07:00
Alex Forencich	f673470cf2	merged changes in eth	2021-03-30 16:20:04 -07:00
Alex Forencich	32abea89fa	Update testbenches	2021-03-06 20:30:25 -08:00
Alex Forencich	c620cd23e7	merged changes in pcie	2021-03-06 20:29:02 -08:00
Alex Forencich	48e1c39e3f	merged changes in eth	2021-03-06 20:27:23 -08:00
Alex Forencich	cd8566a6bc	merged changes in axi	2021-03-06 20:27:13 -08:00
Alex Forencich	d416e9f7fa	Roll back PCIe tag count to 64	2021-03-05 14:04:52 -08:00
Alex Forencich	705133bf7a	Add SPI interface to Gecko BMC on fb2CG@KU15P	2021-03-04 22:34:52 -08:00
Alex Forencich	a644d6dd3f	Update Vivado makefiles	2021-03-01 23:05:37 -08:00
Alex Forencich	d0b19efce5	Reconcile PCIe changes	2021-03-01 00:25:15 -08:00
Alex Forencich	421dbd5d0f	merged changes in pcie	2021-03-01 00:03:44 -08:00
Alex Forencich	a3c104f7dd	Connect write done signals	2021-02-24 15:07:26 -08:00
Alex Forencich	65fdc332b3	merged changes in pcie	2021-02-24 15:03:37 -08:00
Alex Forencich	365d39990d	merged changes in eth	2021-02-24 15:03:24 -08:00
Alex Forencich	6bc757dbc0	merged changes in axi	2021-02-24 15:03:08 -08:00
Alex Forencich	4b3d153cbd	Add placement constraints for fb2CG@KU15P	2021-02-23 02:33:37 -08:00
Alex Forencich	2779087de9	Constrain DMA muxes to same SLR	2021-02-23 02:17:10 -08:00
Alex Forencich	ceebb9f20e	Add more PCIe-related components to PCIe pblock	2021-02-23 00:55:05 -08:00
Alex Forencich	6ab66ed347	Fix signal name in xdc	2021-02-14 15:08:13 -08:00
Alex Forencich	ea093b0126	More XDC cleanup	2021-02-06 15:15:05 -08:00