341 Commits

Author	SHA1	Message	Date
Alex Forencich	e230fecb23	XDC clean up	2020-07-13 23:58:39 -07:00
Alex Forencich	9b7fa688d5	Add 100G mqnic design for Alveo U280	2020-07-12 11:33:28 -07:00
Alex Forencich	6433275139	Add 10G mqnic design for Alveo U280	2020-07-12 11:33:18 -07:00
Alex Forencich	f99736d4f5	Convert to TCL IP	2020-07-11 20:07:13 -07:00
Alex Forencich	5dd5f8bb3e	merged changes in pcie	2020-07-10 19:46:48 -07:00
Alex Forencich	7c10036183	merged changes in eth	2020-07-10 19:46:43 -07:00
Alex Forencich	0ff6282ed6	merged changes in axi	2020-07-10 19:46:37 -07:00
Alex Forencich	4e958096b2	Update driver model to set MTU registers	2020-05-01 19:19:56 -07:00
Alex Forencich	ae775a9386	Rewrite RX buffer management	2020-05-01 19:00:58 -07:00
Alex Forencich	8b535e54ac	Add MTU registers	2020-05-01 18:55:01 -07:00
Alex Forencich	ca0cbf4d93	Update parameters	2020-05-01 17:22:21 -07:00
Alex Forencich	1f76606667	Move TDMA registers	2020-05-01 16:55:57 -07:00
Alex Forencich	ded213460d	Rewrite TX buffer management	2020-05-01 14:29:52 -07:00
Alex Forencich	1c7b7937e5	Limit in-flight descriptor requests in TX engine	2020-04-30 23:37:41 -07:00
Alex Forencich	45ec6657b1	Limit in-flight descriptor requests in RX engine	2020-04-30 23:29:43 -07:00
Alex Forencich	31cec8d0c1	Fix cmac_pad frame truncation bug	2020-04-22 23:23:34 -07:00
Alex Forencich	9e64d19ea5	Use scatter descriptor blocks in driver model	2020-04-21 01:04:07 -07:00
Alex Forencich	2c6e9673f7	Add log_desc_block_size ring parameter in driver model	2020-04-21 00:58:12 -07:00
Alex Forencich	e14cfa0a58	Update port and interface modules	2020-04-20 21:25:21 -07:00
Alex Forencich	7087a595e9	Update RX and TX engines to support descriptor blocks	2020-04-20 21:24:25 -07:00
Alex Forencich	0fb60d718d	Add log desc block size to desc_fetch module	2020-04-20 21:01:55 -07:00
Alex Forencich	d0cf549057	Add log desc block size field to queue manager	2020-04-20 20:45:10 -07:00
Alex Forencich	50af74aa88	Change QUEUE_LOG_SIZE_WIDTH to LOG_QUEUE_SIZE_WIDTH	2020-04-20 18:43:26 -07:00
Alex Forencich	105a834790	Add mqnic design for NetFPGA SUME	2020-03-28 00:44:04 -07:00
Alex Forencich	9e3e80661c	Use common sync_reset module	2020-03-27 23:53:05 -07:00
Alex Forencich	c364bab778	merged changes in eth	2020-03-27 19:08:47 -07:00
Alex Forencich	3786cf0ca3	merged changes in pcie	2020-03-26 17:25:23 -07:00
Alex Forencich	ec03a36f98	Add 100G mqnic design for VCU118	2020-03-25 23:02:36 -07:00
Alex Forencich	309ee212bc	merged changes in pcie	2020-03-24 23:25:56 -07:00
Alex Forencich	a196cd227c	Enable bus mastering and MSI in driver model	2020-03-12 15:32:08 -07:00
Alex Forencich	457f4d7f3f	Use configured ring stride	2020-03-12 15:28:00 -07:00
Alex Forencich	0c32192226	Use constants instead of magic numbers	2020-03-12 15:08:20 -07:00
Alex Forencich	1216f7a76e	Offset packet start by 10 bytes to match Linux kernel skb alignment	2020-03-08 21:56:08 -07:00
Alex Forencich	23aef37aff	Rewrite resets	2020-03-08 16:56:06 -07:00
Alex Forencich	24eae58e6c	merged changes in pcie	2020-03-08 15:25:28 -07:00
Alex Forencich	248a0b4f93	Convert descriptor to DMA operation without storing in table	2020-03-08 00:22:55 -08:00
Alex Forencich	f7a1a7ef95	Add descriptor FIFOs	2020-03-07 22:28:59 -08:00
Alex Forencich	4dd5104f4d	Stripe completion queues across event queues	2020-03-06 00:58:30 -08:00
Alex Forencich	627153cd9b	Fix signal sizing bug	2020-03-06 00:24:13 -08:00
Alex Forencich	2b14ab2555	Update cmac_pad to pad frames to 60 bytes	2020-02-26 13:36:19 -08:00
Alex Forencich	7ebdceedf2	merged changes in pcie	2020-02-26 13:34:53 -08:00
Alex Forencich	239b7ddd0b	Add missing QSFP lpmode connections	2020-02-03 13:52:29 -08:00
Alex Forencich	63fcadaf0f	Add missing refclk control connections	2020-01-30 12:22:44 -08:00
Alex Forencich	2f595be70e	merged changes in pcie	2020-01-24 13:52:45 -08:00
Alex Forencich	70450a4d89	Add 100G mqnic design for VCU1525	2020-01-16 23:36:32 -08:00
Alex Forencich	26b7b67b9b	Add 10G mqnic design for VCU1525	2020-01-16 23:35:00 -08:00
Alex Forencich	e7cadac773	Remove extraneous files	2019-12-31 22:35:25 -08:00
Alex Forencich	81842e3c50	Add 100G mqnic design for Alpha Data board	2019-12-31 21:43:39 -08:00
Alex Forencich	217217b45e	Remove unused table fields	2019-12-30 22:02:22 -08:00
Alex Forencich	f642bb7f7e	Reserve packet data slot early and release on dequeue fail	2019-12-30 17:49:42 -08:00