11 Commits

Author	SHA1	Message	Date
Alex Forencich	4f1eabab17	Split async FIFO resets	2021-10-13 14:05:13 -07:00
Alex Forencich	b7f3faa628	Add timing constraints for Quartus Prime Pro	2021-05-18 16:02:36 -07:00
Alex Forencich	e9f7723312	Reorganize timing constraints	2021-05-16 23:28:00 -07:00
Alex Forencich	da152a8546	Update timing parameters for async FIFO to reflect new pipeline register naming	2020-09-07 18:54:32 -07:00
Alex Forencich	71bd4a1811	Add SDC constraints for Quartus	2020-07-10 14:02:08 -07:00
Alex Forencich	fd1ec1690f	Add sync_reset module and timing constraints	2020-03-27 18:04:04 -07:00
Alex Forencich	ced2df141c	Add false path for async FIFO implementation in distributed RAM	2019-06-10 17:40:30 -07:00
Alex Forencich	75d9154d32	Reduce extraneous warnings from get_cells	2019-06-10 17:39:18 -07:00
Alex Forencich	ad3905ac4d	Account for more merged registers	2019-03-28 16:33:01 -07:00
Alex Forencich	e938844783	Account for merged registers	2019-03-27 23:54:48 -07:00
Alex Forencich	48984013de	Add AXI stream async FIFO timing constraints	2019-03-26 18:46:25 -07:00