Alex Forencich
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4fa3870dea
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Remove string parameters
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2021-06-02 15:08:43 -07:00 |
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Alex Forencich
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892ee84bff
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Delay command until write is acknowledged
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2021-05-31 01:32:02 -07:00 |
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Alex Forencich
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3579310447
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Clear active bit
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2021-05-31 01:31:30 -07:00 |
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Alex Forencich
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34d5a4fed5
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Add wrapper generator for RAM switch
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2021-05-30 12:32:26 -07:00 |
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Alex Forencich
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16b174b490
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Print addressing configuration
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2021-05-30 12:19:01 -07:00 |
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Alex Forencich
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e3183862bb
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tkeep always active inside RAM switch
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2021-05-30 12:12:10 -07:00 |
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Alex Forencich
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56a3b8fe92
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Fix indexed part select error in degenerate case when M_COUNT = 1
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2021-05-30 12:11:46 -07:00 |
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Alex Forencich
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8e5c4874eb
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Fix switch wrapper parameters
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2021-05-30 12:10:04 -07:00 |
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Alex Forencich
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9d99ec0096
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Update wrapper generators
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2021-04-03 16:34:42 -07:00 |
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Alex Forencich
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3df18fafdd
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Use nonblocking assignment
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2021-04-03 16:33:45 -07:00 |
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Alex Forencich
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d834e49587
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Move wire declarations
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2020-12-03 17:37:53 -08:00 |
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Alex Forencich
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1f9aa62639
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Add wrapper generator for axis_broadcast
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2020-12-03 17:31:11 -08:00 |
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Alex Forencich
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71b6b9f6f2
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Prevent shift register inference
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2020-09-07 18:54:18 -07:00 |
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Alex Forencich
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ede73b434a
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Add PIPELINE_OUTPUT parameter to FIFO adapter modules
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2020-09-07 00:22:55 -07:00 |
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Alex Forencich
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2f883681d6
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Add pararametrizable output pipeline to FIFOs
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2020-09-07 00:14:22 -07:00 |
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Alex Forencich
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eb6861cbc4
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Convert to single always block
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2020-09-06 22:57:56 -07:00 |
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Alex Forencich
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c9950d56ae
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Rewrite full/empty logic
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2020-09-06 18:28:32 -07:00 |
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Alex Forencich
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b7ed61b242
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Rewrite resets
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2020-09-06 17:55:10 -07:00 |
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Alex Forencich
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84cffeca5f
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Remove unneeded address registers
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2020-09-06 17:52:41 -07:00 |
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Alex Forencich
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a7689b6772
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Pipeline RAM output in RAM switch
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2020-09-03 15:55:45 -07:00 |
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Alex Forencich
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ae10935a93
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Rewrite priority encoder to remove recusive construction
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2020-08-17 18:29:05 -07:00 |
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Alex Forencich
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4754d94736
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Fix backpressure bug
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2020-04-17 21:22:07 -07:00 |
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Alex Forencich
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fd1ec1690f
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Add sync_reset module and timing constraints
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2020-03-27 18:04:04 -07:00 |
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Alex Forencich
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f9915b2f31
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Refactor
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2020-02-19 21:32:00 -08:00 |
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Alex Forencich
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406a3d69d1
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Rework read handling
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2020-02-19 21:24:15 -08:00 |
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Alex Forencich
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2876235a72
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Throughput optimizations
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2020-02-19 18:15:58 -08:00 |
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Alex Forencich
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52d1117753
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Add AXI stream RAM switch module and testbenches
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2020-02-18 01:06:14 -08:00 |
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Alex Forencich
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a9c04a4651
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Fix frame FIFO drop
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2019-10-24 12:08:08 -07:00 |
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Alex Forencich
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6795c25e7f
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Fix use before define
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2019-08-09 18:05:32 -07:00 |
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Alex Forencich
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ce00df8de1
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Include instance names in error messages
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2019-07-25 16:30:10 -07:00 |
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Alex Forencich
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0a85a4a2aa
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Fix assert
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2019-07-25 00:43:42 -07:00 |
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Alex Forencich
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592ae7e6a2
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Change default switch addressing to use MSBs of tdest
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2019-07-25 00:40:13 -07:00 |
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Alex Forencich
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76c805e416
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Fix more indexing bugs
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2019-07-24 15:38:49 -07:00 |
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Alex Forencich
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23b9490fac
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Fix switch bug
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2019-07-24 15:22:35 -07:00 |
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Alex Forencich
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5f454d6c05
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Update axis_switch to support default routing configurations
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2019-07-24 14:20:07 -07:00 |
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Alex Forencich
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c5f44c70d1
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Add parameter documentation
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2019-07-24 13:54:21 -07:00 |
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Alex Forencich
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c091f7ed76
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Add switch wrapper generator
|
2019-07-24 13:46:33 -07:00 |
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Alex Forencich
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b4cebd8394
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Fix crosspoint wrapper generator
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2019-07-24 13:44:43 -07:00 |
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Alex Forencich
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c759ff03b7
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Fix default parameter
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2019-07-24 11:07:17 -07:00 |
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Alex Forencich
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69de6fd2a4
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Convert FIFOs to use DEPTH parameter instead of ADDR_WIDTH
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2019-07-18 11:27:25 -07:00 |
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Alex Forencich
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e0a1a73ce0
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Mask tdata with tkeep
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2019-07-18 11:01:00 -07:00 |
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Alex Forencich
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ccc15324a6
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Fix bad frame mask
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2019-06-09 18:46:49 -07:00 |
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Alex Forencich
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8e969aa14c
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Add FIFO/width adapter wrapper modules
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2019-04-26 18:38:25 -07:00 |
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Alex Forencich
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a9c7946368
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Change parameter concatenation to increments of DEST_WIDTH
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2019-03-28 23:49:04 -07:00 |
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Alex Forencich
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932aa35451
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Fix AXI stream async frame FIFO write pointer synchronization
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2019-03-26 18:45:54 -07:00 |
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Alex Forencich
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88badf13f0
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Reset all status synchronization stages
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2019-03-26 16:19:49 -07:00 |
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Alex Forencich
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414f091c2c
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Properly handle width of 1
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2019-03-07 22:59:49 -08:00 |
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Alex Forencich
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b1f3a74b86
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Remove unused code
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2019-03-07 22:59:15 -08:00 |
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Alex Forencich
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d2df971fc9
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Add AXI stream frame length measurement module and testbenches
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2019-03-07 22:57:46 -08:00 |
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Alex Forencich
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b60886a0ec
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Add AXI stream broadcast module and testbench
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2019-02-27 19:46:30 -08:00 |
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