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288 Commits 1 Branch 0 Tags
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196 Commits

Author SHA1 Message Date
Alex Forencich
8d9ed665d7 Use logical operator instead of bitwise 2018-12-09 00:04:56 -08:00
Alex Forencich
cadd1bcb50 Match width 2018-12-09 00:04:30 -08:00
Alex Forencich
aa6991a4a5 Bitwise operators instead of generate 2018-12-09 00:03:09 -08:00
Alex Forencich
3d90e80da8 Fix frame FIFO full logic bug 2018-12-09 00:01:38 -08:00
Alex Forencich
f45a3ef5e0 Change cycle to segment 2018-12-03 12:40:06 -08:00
Alex Forencich
a72d7bd260 Fix generate statement 2018-11-28 14:18:09 -08:00
Alex Forencich
8d564b1074 Convert localparam to parameter as Vivado does not like clog2 in localparams 2018-10-30 17:35:38 -07:00
Alex Forencich
be51f2b472 Update FIFO instantiations 2018-10-25 16:06:32 -07:00
Alex Forencich
ded363b471 Rename status outputs 2018-10-25 15:36:34 -07:00
Alex Forencich
ed4a2d73c2 Add axis_pipeline_register module 2018-10-25 14:29:35 -07:00
Alex Forencich
312d90addb Add wrapper generators 2018-10-25 14:23:00 -07:00
Alex Forencich
e9d9f32150 Rename ports 2018-10-25 12:00:34 -07:00
Alex Forencich
6f4ab8f180 Rename ports 2018-10-25 11:59:13 -07:00
Alex Forencich
84a758f100 Rename ports 2018-10-25 11:56:52 -07:00
Alex Forencich
6c1ea89a66 Rename ports 2018-10-25 11:52:08 -07:00
Alex Forencich
fd28040c40 Rename ports 2018-10-25 11:30:35 -07:00
Alex Forencich
7997a4a844 Rename ports 2018-10-25 11:19:28 -07:00
Alex Forencich
8d9da455cd Minor optimizations 2018-10-25 10:29:31 -07:00
Alex Forencich
cb9f2132a4 Update parameter ordering 2018-10-25 10:20:17 -07:00
Alex Forencich
09a8fa51b6 Rename ports 2018-10-25 10:19:32 -07:00
Alex Forencich
c47f3ea03d Update FIFO instance, rename ports 2018-10-25 10:17:58 -07:00
Alex Forencich
d1ed1528b5 Update FIFO instance, rename ports 2018-10-25 10:15:16 -07:00
Alex Forencich
11d9dbe24a Merge axis_async_fifo and axis_async_frame_fifo, rename ports 2018-10-25 09:53:38 -07:00
Alex Forencich
36d0a8786f Merge axis_fifo and axis_frame_fifo, rename ports 2018-10-24 23:16:06 -07:00
Alex Forencich
2bb9f11c9e Use logical operators 2018-10-24 22:24:27 -07:00
Alex Forencich
9d813226d0 Convert generated demux to verilog parametrized demux 2018-10-24 22:16:05 -07:00
Alex Forencich
145ea2c40c Connect arbiter parameters to top level 2018-10-24 21:09:00 -07:00
Alex Forencich
2bf15706cd Convert generated mux to verilog parametrized mux 2018-10-24 18:23:14 -07:00
Alex Forencich
029d1fa06f Fix loop count variable scoping issue 2018-10-24 17:58:39 -07:00
Alex Forencich
fc6c07e5f9 Convert generated frame joiner to verilog parametrized frame joiner 2018-10-24 17:07:22 -07:00
Alex Forencich
fd7f65d5ad Convert generated switch to verilog parametrized switch 2018-10-24 16:12:56 -07:00
Alex Forencich
631147069f Rename ports and add reg_type parameter to axis_register 2018-10-24 14:35:08 -07:00
Alex Forencich
940c1210c1 Convert arbitrated mux to verilog parametrized arbitrated mux 2018-10-24 13:49:17 -07:00
Alex Forencich
fe77db822d Convert generated crosspoint to verilog parametrized crosspoint 2018-10-24 13:44:39 -07:00
Alex Forencich
8e5ec36ced Optimize axis_arb_mux and improve latency 2018-08-09 18:40:50 -07:00
Alex Forencich
7a879aec1c Remove extra registers 2018-08-09 18:38:41 -07:00
Alex Forencich
202fbcbb6f Fix typo 2018-08-09 11:23:27 -07:00
Alex Forencich
7c6da337b0 Happy new year 2018-02-27 01:39:25 -08:00
Alex Forencich
5df7efe516 Happy new year 2018-02-26 12:25:20 -08:00
Alex Forencich
4ec4c901e8 Whitespace fixes 2017-11-21 00:18:09 -08:00
Alex Forencich
b00eaf4d3c Add tkeep signal and update testbench for stat counter 2017-11-21 00:17:42 -08:00
Alex Forencich
ad0e3e1eb5 Whitespace fixes and testbench update for frame joiner 2017-11-21 00:16:15 -08:00
Alex Forencich
a1a6d523e3 Update FIFO instances and testbenches for COBS encoder and decoder 2017-11-21 00:14:26 -08:00
Alex Forencich
0edafd58ac Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream tap 2017-11-20 23:45:34 -08:00
Alex Forencich
4ef4ef2622 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream SRL register 2017-11-20 21:34:25 -08:00
Alex Forencich
b0d7820f5b Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream SRL FIFO 2017-11-20 21:32:46 -08:00
Alex Forencich
d16f19f67e Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream rate limiter 2017-11-20 21:31:41 -08:00
Alex Forencich
772e433ee9 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream frame length adjuster 2017-11-20 21:30:26 -08:00
Alex Forencich
de590517a9 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream switch 2017-11-20 20:17:20 -08:00
Alex Forencich
91a7169f46 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream crosspoint 2017-11-20 20:16:21 -08:00