41 Commits

Author	SHA1	Message	Date
Alex Forencich	092c72ba66	Compute req_last_tlp in advance	2020-02-27 18:19:45 -08:00
Alex Forencich	18bf537f4f	Fix register size	2020-02-27 15:47:18 -08:00
Alex Forencich	a00589e5a3	Timing optimizations	2020-02-27 15:24:24 -08:00
Alex Forencich	ec2ceb8e56	Timing optimizations	2020-01-24 13:51:30 -08:00
Alex Forencich	7567db1818	Add credit-based flow control to DMA cores	2019-12-06 23:24:36 -08:00
Alex Forencich	60a2813fbc	Fix indentation	2019-12-05 22:09:04 -08:00
Alex Forencich	546ef162dd	Rewrite reset	2019-11-26 16:44:46 -08:00
Alex Forencich	4c8fcef230	Add RQ sequence number inputs, TX_LIMIT parameter to ultrascale read DMA modules	2019-11-26 16:30:30 -08:00
Alex Forencich	bbcdcc17bc	Rename OP_TAG_WIDTH to OP_TABLE_SIZE	2019-11-25 14:59:53 -08:00
Alex Forencich	ee532a2472	Check tag count based on target device	2019-11-15 14:57:23 -08:00
Alex Forencich	52c502227f	Remove unused client tag ports and parameters	2019-11-15 00:55:13 -08:00
Alex Forencich	553d7e05fe	Update AXI DMA modules to support 512 bit interface	2019-10-14 16:22:09 -07:00
Alex Forencich	a92722173a	Handle ultrascale plus interface widths	2019-10-04 16:29:11 -07:00
Alex Forencich	7197e17445	Remove redundant code	2019-09-29 12:57:48 -07:00
Alex Forencich	e97e4ad423	Parametrize tuser signal widths	2019-09-26 23:30:03 -07:00
Alex Forencich	8678ecee65	Fix bug in AXI operation generation	2019-09-26 23:25:09 -07:00
Alex Forencich	e365ae44da	Move AXI transfer size logic to improve timing	2019-09-26 14:39:31 -07:00
Alex Forencich	68974e800b	Fix completion handling bug	2019-08-19 14:31:08 -07:00
Alex Forencich	f518aec219	Include instance names in error messages	2019-07-25 16:38:54 -07:00
Alex Forencich	c75f29c648	Add parameter documentation	2019-07-24 18:01:13 -07:00
Alex Forencich	0515d354e3	Critical path optimization	2019-06-28 17:28:12 -07:00
Alex Forencich	4afbd71f1f	Fanout optimization	2019-06-28 17:24:37 -07:00
Alex Forencich	db8a2e1e96	Parametrize cycle count widths	2019-05-13 22:06:41 -07:00
Alex Forencich	74a75772ec	Pipeline tag table write	2019-05-13 19:15:43 -07:00
Alex Forencich	c1c4971d73	Use correct variable	2019-04-09 17:54:04 -07:00
Alex Forencich	5d42112477	Enable PCIe extended tag based on tag count	2019-03-21 00:01:48 -07:00
Alex Forencich	56ebc966e1	Update parameters	2019-03-03 13:37:34 -08:00
Alex Forencich	201c5faa80	Always ready on RC channel in idle for 64 bits	2019-01-22 23:00:17 -08:00
Alex Forencich	4422b908bf	Backpressure for awvalid	2019-01-22 22:54:40 -08:00
Alex Forencich	fac972bfe6	RC channel backpressure fix	2019-01-22 22:50:15 -08:00
Alex Forencich	263bb5c670	Index based on correct tag value	2019-01-22 22:47:15 -08:00
Alex Forencich	d86fb594c5	More fixes for tlp_cmd backpressure	2019-01-12 00:37:38 -08:00
Alex Forencich	5c24dcc1df	Ensure tlp_cmd registers are clear when generating a new request	2019-01-11 01:27:52 -08:00
Alex Forencich	5cf9597201	Only generate a request if a tag is available	2019-01-10 19:00:19 -08:00
Alex Forencich	9b572ad0ac	Fix bug	2019-01-02 01:59:05 -08:00
Alex Forencich	fbec32e4f2	Use whole status FIFO memory	2018-12-06 17:36:12 -08:00
Alex Forencich	5db9cddf6e	Reorganize and simplify burst length computation code	2018-11-29 15:20:01 -08:00
Alex Forencich	8ab02e4220	Remove some debug code	2018-11-28 11:14:26 -08:00
Alex Forencich	89c8e87f95	Add status FIFO to manage write responses	2018-11-28 11:13:53 -08:00
Alex Forencich	c6f342ef01	Respect enable signal	2018-11-28 01:18:48 -08:00
Alex Forencich	28fa143ae5	Add Ultrascale PCIe DMA modules and testbenches	2018-11-26 23:23:54 -08:00