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Author SHA1 Message Date
Alex Forencich
ede33bb23e lib/mqnic: Add statistics counter read support to userspace library 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-23 17:38:18 -08:00
Alex Forencich
3daeb18d5f lib/mqnic: Refactor clock info register block code in userspace library 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-23 17:37:45 -08:00
Alex Forencich
61caf147f7 Use CMAC wrapper in 100G mqnic design for XUP-P3R 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 18:26:10 -08:00
Alex Forencich
596db2d756 Use CMAC wrapper in 100G mqnic design for VCU118 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 18:24:43 -08:00
Alex Forencich
db621ffa7d Use CMAC wrapper in 100G mqnic design for 250-SoC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 18:01:43 -08:00
Alex Forencich
cdda035427 Use CMAC wrapper in 100G mqnic design for VCU1525 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 17:35:09 -08:00
Alex Forencich
e51e5a84af Use CMAC wrapper in 100G mqnic design for Alveo U50 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 17:07:12 -08:00
Alex Forencich
39c5744e99 Use CMAC wrapper in 100G mqnic design for Alveo U280 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 16:30:55 -08:00
Alex Forencich
3d993e4479 Use CMAC wrapper in 100G mqnic design for Alveo U250 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 16:00:45 -08:00
Alex Forencich
f67bd98719 Use CMAC wrapper in 100G mqnic design for Alveo U200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 12:38:14 -08:00
Alex Forencich
49be896333 Use CMAC wrapper in 100G mqnic design for ADM-PCIE-9V3 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 11:49:34 -08:00
Alex Forencich
f70f4d9b90 Use CMAC wrapper in 100G mqnic design for fb2CG@KU15P 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 11:42:07 -08:00
Alex Forencich
bf7cf3fef9 Add CMAC wrapper 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-09 20:58:30 -08:00
Alex Forencich
f6262c3606 fpga/mqnic: Update FIFO parameter naming 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 23:57:50 -07:00
Alex Forencich
0cb106e2aa merged changes in eth 2022-11-01 23:57:35 -07:00
Alex Forencich
2199a15c75 Force possible floating point parameter value to integer when taking clog2 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 23:56:27 -07:00
Alex Forencich
5e528e0057 Update FIFO PIPELINE_OUTPUT to RAM_PIPELINE 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 23:56:11 -07:00
Alex Forencich
b765c78f56 merged changes in axis 2022-11-01 23:55:36 -07:00
Alex Forencich
ed6130575d Update async FIFO timing constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 23:27:39 -07:00
Alex Forencich
9c3409f9d7 Add option for output FIFO to improve pipelining and RAM inference for large FIFOs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 19:02:53 -07:00
Alex Forencich
d4cf84ccf0 Consolidated RAM pipeline output wires 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 16:36:11 -07:00
Alex Forencich
6f761bc4a5 Use separate RAM output register for better pipeline register inference 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 14:46:24 -07:00
Alex Forencich
a0f46801a1 Replace OUTPUT_PIPELINE with RAM_PIPELINE 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 14:40:58 -07:00
Alex Forencich
fa4e8e70cb Add intermediate signal for end of FIFO RAM pipeline 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 14:03:51 -07:00
Alex Forencich
e542d39a75 Fix assignment type 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-20 09:21:34 -07:00
Alex Forencich
8c733dff9e fpga/mqnic/fb2CG: Update placement constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-17 13:01:16 -07:00
Alex Forencich
e3f2d8990d fpga/mqnic: Use all ports for TDMA designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-15 23:30:54 -07:00
Alex Forencich
b19ff209da fpga/common: More parameter cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-15 23:30:17 -07:00
Alex Forencich
d3942da875 fpga: Add clock info register block 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-15 19:45:02 -07:00
Alex Forencich
6fa30bc94c fpga/mqnic: Fix critical warnings when MIGs are not present 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-15 13:47:41 -07:00
Alex Forencich
d0cc106783 fpga: Remove redundant RX_RSS_ENABLE parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-13 17:10:25 -07:00
Alex Forencich
2714ba5cdd merged changes in pcie 2022-10-12 23:57:47 -07:00
Alex Forencich
01df80df86 fpga/mqnic: Disable MIGs by default 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 23:57:27 -07:00
Alex Forencich
6bfaef78bd Properly handle 4KB read requests in UltraScale shim 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 21:52:27 -07:00
Alex Forencich
633037d032 Fix direction of config signals 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 21:40:08 -07:00
Alex Forencich
5e396ceb87 Rename seg_rc_hdr to seg_rq_hdr 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 21:19:48 -07:00
Alex Forencich
5e52a52f5e fpga/mqnic: Add MIGs and HBM controllers for most boards 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 19:00:49 -07:00
Alex Forencich
941288e926 fpga/common: Add AXI interfaces for DDR and HBM to core logic and application section 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 17:12:23 -07:00
Alex Forencich
eb990643f2 fpga/mqnic: various minor cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 17:12:07 -07:00
Alex Forencich
5f1e74b0e1 Add PROJECT variable, remove multiple stem matches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-11 13:33:09 -07:00
Alex Forencich
7017e7d49b Explicitly set top module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-11 12:29:01 -07:00
Alex Forencich
ceb6a9ca06 Update clean target 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-11 12:26:39 -07:00
Alex Forencich
9c98f12392 Write debug probes file alongside bit file 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-10 23:37:54 -07:00
Alex Forencich
9628401780 Normalize output file location 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-10 21:47:53 -07:00
Alex Forencich
caf2a0993b fpga: Output hierarchical utilization reports 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-06 21:17:25 -07:00
Alex Forencich
fe37e4a4bb fpga/common: Use correct parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-06 21:15:26 -07:00
Alex Forencich
62711295e0 Update pcie_if model 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-27 15:28:07 -07:00
Alex Forencich
56fe10f27d fpga/common: Fix lost TX request status issue in transmit engine 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-21 15:20:27 -07:00
Alex Forencich
efbeecde35 fpga/common: Clean up parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-21 15:19:49 -07:00
Alex Forencich
ebbddb5559 fpga/common: Add multiple queue test to core testbenches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-20 21:59:02 -07:00