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573 Commits 1 Branch 0 Tags
Commit Graph

69 Commits

Author SHA1 Message Date
Alex Forencich
52058cb5de Swap out PHY in VCU118 example design 2019-02-05 18:28:42 -08:00
Alex Forencich
5f6e7f721c Update testbench 2019-01-31 18:12:07 -08:00
Alex Forencich
07b4efa9ba Switch out Xilinx PHY core in ExaNIC X10 example design 2019-01-18 13:49:46 -08:00
Alex Forencich
0bbe062c66 Switch out Xilinx PHY core in ADM-PCIE-9V3 example design 2019-01-18 13:32:58 -08:00
Alex Forencich
2e29aea857 Fix input clock period settings 2019-01-17 19:09:47 -08:00
Alex Forencich
b8b504682a Fix transceiver clocking 2019-01-15 00:30:36 -08:00
Alex Forencich
6d52a7c0e7 Remove unneeded links 2019-01-08 17:31:49 -08:00
Alex Forencich
2628249059 Add ADM-PCIE-9V3 example design 2019-01-08 17:27:21 -08:00
Alex Forencich
1f793fa7d0 Update readme 2019-01-08 17:24:22 -08:00
Alex Forencich
82454e4ae1 Add ExaNIC X10 example design 2019-01-08 17:22:01 -08:00
Alex Forencich
e882ed143f Update example designs 2018-11-08 09:20:33 -08:00
Alex Forencich
0a6bee6d69 Update example designs 2018-11-08 09:17:29 -08:00
Alex Forencich
7d6889add6 Update example designs 2018-10-30 21:32:32 -07:00
Alex Forencich
00dc50826d Update example designs 2018-10-24 01:03:44 -07:00
Alex Forencich
030fe90bf5 Fix example design testbench 2018-10-19 15:33:25 -07:00
Alex Forencich
8982b4f4e1 Fix modsell pin 2018-06-29 13:00:41 -07:00
Alex Forencich
cd51821bf7 Add parameters 2018-06-22 18:56:05 -07:00
Alex Forencich
6368529b6f Add clock frequency annotation 2018-06-14 13:42:10 -07:00
Alex Forencich
e4672915e6 Update testbenches to use instances() 2018-06-13 22:43:11 -07:00
Alex Forencich
298ae4defa Update MAC module instantiation 2018-06-13 22:16:02 -07:00
Alex Forencich
8e1f14e9a7 Add VCU118 10G example design 2018-06-13 19:30:07 -07:00
Alex Forencich
05c6743473 Update xdc 2018-06-13 19:18:59 -07:00
Alex Forencich
f4d7edf23f Add VCU118 example design 2018-06-13 14:33:07 -07:00
Alex Forencich
415f723edc Fix clock name 2018-06-11 16:37:34 -07:00
Alex Forencich
c31757552b Add crosspoint design 2018-05-31 16:27:56 -07:00
Alex Forencich
855b593ce5 Minor updates to 10G example designs 2018-05-31 16:05:41 -07:00
Alex Forencich
0fd157964a Happy new year 2018-02-26 12:50:51 -08:00
Alex Forencich
3063a761e5 Support both versions of ML605 2018-02-26 00:18:14 -08:00
Alex Forencich
bd27156f35 AXI stream updates 2018-02-26 00:08:08 -08:00
Alex Forencich
cf6a01fffe Add ML605 SGMII design 2017-07-22 11:07:23 -07:00
Alex Forencich
eb47bea9a1 Use correct clock in testbench 2017-06-09 21:28:08 -07:00
Alex Forencich
69253d2d83 Update VCU108 example design 2017-06-01 06:48:50 -07:00
Alex Forencich
1b6816b06f Add ML605 RGMII example design 2017-05-31 20:24:43 -07:00
Alex Forencich
de00b3e233 Rename ML605 example design 2017-05-31 20:06:32 -07:00
Alex Forencich
e376c805d2 Update ML605 reference design 2017-05-31 19:52:43 -07:00
Alex Forencich
9fdc36450a Update NexysVideo reference design 2017-05-31 19:44:39 -07:00
Alex Forencich
a8a423da0e Update Atlys example design 2017-05-31 19:35:40 -07:00
Alex Forencich
0fc986041e Fix example design LED logic 2017-05-19 17:44:29 -07:00
Alex Forencich
57a16b7d54 Add ML605 example design 2017-05-19 17:33:07 -07:00
Alex Forencich
2e3b15239b Update Vivado IP 2017-05-18 13:49:10 -07:00
Alex Forencich
9b2ac9dfc1 Happy new year 2017-05-18 13:47:45 -07:00
Alex Forencich
c2e459c971 Connect transceiver control lines 2017-03-09 17:14:14 -08:00
Alex Forencich
3b47b422fa Fix Vivado clock groups 2016-10-06 17:52:23 -07:00
Alex Forencich
77ecbd7dcb Makefile updates 2016-10-05 17:41:00 -07:00
Alex Forencich
270641b7a3 Update UDP modules and example designs to utilize UDP checksum modules 2016-09-30 22:15:21 -07:00
Alex Forencich
15330486e8 Convert GMII and RGMII shims to use generic IO components 2016-09-29 20:10:10 -07:00
Alex Forencich
88150c9d5f Update and rework endpoints, update testbenches 2016-09-13 15:24:02 -07:00
Alex Forencich
36af29db77 Add i2c init code for si570 reference oscillator 2016-08-03 14:44:10 -04:00
Alex Forencich
833d1dac81 Route 10G link status to LEDs 2016-07-28 09:57:36 -04:00
Alex Forencich
2365f4b6fc Connect QSFP module control pins 2016-07-28 09:56:13 -04:00