21 Commits

Author	SHA1	Message	Date
Alex Forencich	0a6bee6d69	Update example designs	2018-11-08 09:17:29 -08:00
Alex Forencich	7d6889add6	Update example designs	2018-10-30 21:32:32 -07:00
Alex Forencich	e4672915e6	Update testbenches to use instances()	2018-06-13 22:43:11 -07:00
Alex Forencich	298ae4defa	Update MAC module instantiation	2018-06-13 22:16:02 -07:00
Alex Forencich	0fd157964a	Happy new year	2018-02-26 12:50:51 -08:00
Alex Forencich	bd27156f35	AXI stream updates	2018-02-26 00:08:08 -08:00
Alex Forencich	eb47bea9a1	Use correct clock in testbench	2017-06-09 21:28:08 -07:00
Alex Forencich	a8a423da0e	Update Atlys example design	2017-05-31 19:35:40 -07:00
Alex Forencich	0fc986041e	Fix example design LED logic	2017-05-19 17:44:29 -07:00
Alex Forencich	9b2ac9dfc1	Happy new year	2017-05-18 13:47:45 -07:00
Alex Forencich	270641b7a3	Update UDP modules and example designs to utilize UDP checksum modules	2016-09-30 22:15:21 -07:00
Alex Forencich	15330486e8	Convert GMII and RGMII shims to use generic IO components	2016-09-29 20:10:10 -07:00
Alex Forencich	88150c9d5f	Update and rework endpoints, update testbenches	2016-09-13 15:24:02 -07:00
Alex Forencich	b38c643384	Add more implementation parameters to gmii_phy_if	2016-06-28 19:35:52 -07:00
Alex Forencich	47ca9a8725	Replace eth_crc modules for generic lfsr module	2016-06-28 17:31:58 -07:00
Alex Forencich	c5b6202174	Update example design	2016-01-08 01:32:04 -08:00
Alex Forencich	6b23d83361	Set FIFO size in example design	2015-05-08 01:45:42 -07:00
Alex Forencich	6a012c992b	Update example design to use FIFO wrapper	2015-05-08 00:45:27 -07:00
Alex Forencich	5341987c45	Manage ethernet preamble properly	2015-04-01 19:44:25 -07:00
Alex Forencich	92830f87d8	Update for Python 3	2015-04-01 19:43:54 -07:00
Alex Forencich	d489468776	Add example design for Digilent Atlys board	2015-02-28 20:05:05 -08:00