FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity
110 Commits 1 Branch 0 Tags
Commit Graph

110 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Alex Forencich
52fc34d82e Assume first tkeep bit is always set 2016-07-20 12:36:59 -07:00
Alex Forencich
6fe4a033e5 Add dedicated pipeline registers for RAM addresses that are not reset 2016-06-27 12:25:18 -07:00
Alex Forencich
385c9cc90a Fix Vivado block RAM inference 2016-06-27 12:10:36 -07:00
Alex Forencich
4f66059d21 Adjust constant naming 2016-06-27 11:27:04 -07:00
Alex Forencich
f89620008d Remove reset dependence 2016-06-27 11:26:15 -07:00
Alex Forencich
cab7d367f2 Fix default width 2016-06-27 11:24:36 -07:00
Alex Forencich
be4034071b Happy new year 2016-01-05 00:24:20 -08:00
Alex Forencich
7a9fdb5fc3 Add default case statements to avoid inferring latches 2015-11-09 14:54:14 -08:00
Alex Forencich
0d22a35bd8 Update output registers, remove extraneous resets, fix constant widths 2015-11-08 23:05:38 -08:00
Alex Forencich
0a79f24d3c Do not reset datapath registers in crosspoint switch 2015-11-08 17:27:13 -08:00
Alex Forencich
5fb4cb159b Reorganize register modules 2015-11-08 16:18:29 -08:00
Alex Forencich
0f0ebfb87d Reorganize FIFO modules 2015-11-07 01:15:11 -08:00
Alex Forencich
7ea566e6d2 Update generate scripts to use argparse 2015-10-19 19:15:38 -07:00
Alex Forencich
dcad442e7c Improve timing performance of frame length adjust module 2015-10-19 00:30:50 -07:00
Alex Forencich
364b537312 Synchronize status signals for both clock domains in async frame FIFO 2015-10-09 15:14:54 -07:00
Alex Forencich
382226ad59 Don't accept data until reset is complete 2015-10-08 23:46:59 -07:00
Alex Forencich
90ac361df5 Internal synchronous reset on async FIFOs 2015-10-08 13:03:42 -07:00
Alex Forencich
30a35c3d73 Convert async fifo to common reset 2015-10-08 12:52:51 -07:00
Alex Forencich
ca11618e6d Convert to synchronous resets 2015-10-08 11:26:32 -07:00
Alex Forencich
26b165227c Update for compatibility with older versions of Python 2015-07-14 08:27:49 -07:00
Alex Forencich
120f86f4cf Add SRL FIFO reset tests 2015-07-13 23:15:39 -07:00
Alex Forencich
ac97cffc2b Properly reset all registers 2015-07-13 23:15:09 -07:00
Alex Forencich
dfab866e99 Remove unused reg 2015-07-13 23:09:02 -07:00
Alex Forencich
88f3e97bad Update readme 2015-07-09 11:52:06 -07:00
Alex Forencich
04e4ccc517 Update for compatibility with older version of Python 2015-07-09 11:25:49 -07:00
Alex Forencich
516c50d786 Add FIFO reset tests 2015-07-09 11:13:25 -07:00
Alex Forencich
f387e4c300 Remove unused register 2015-07-09 11:13:12 -07:00
Alex Forencich
6bd7309b9d Properly reset all registers 2015-07-09 11:11:32 -07:00
Alex Forencich
87fe1a561f Add AXI stream tap modules 2015-06-22 14:56:56 -07:00
Alex Forencich
c15761068a Add AXI stream frame length adjust modules 2015-06-05 17:04:10 -07:00
Alex Forencich
3d17cc1cee Adjust rate limiter framing logic 2015-05-12 17:58:09 -07:00
Alex Forencich
e72b93033d Add parameters to axis_stat_counter testbench 2015-05-12 17:54:37 -07:00
Alex Forencich
e65173b7ee Add overflow, bad_frame, and good_frame status outputs to frame FIFOs 2015-05-12 17:52:41 -07:00
Alex Forencich
51e65f5a22 Rework async FIFO resets and synchronization 2015-05-08 01:41:35 -07:00
Alex Forencich
14f2d5e9f7 Add tkeep asserts to AXI stream EP 2015-05-03 00:23:58 -07:00
Alex Forencich
9cca78bc7c Fix last cycle detect logic 2015-04-19 23:33:34 -07:00
Alex Forencich
7795a9182b Remove tristate for state machine inference 2015-04-19 23:08:41 -07:00
Alex Forencich
966e47a826 Fix RAM and register widths 2015-04-19 23:06:30 -07:00
Alex Forencich
9b7bad92f2 Reset pointers correctly 2015-04-19 17:51:27 -07:00
Alex Forencich
8cd0d3ee06 Update .travis.yml 2015-03-21 04:49:43 -07:00
Alex Forencich
eb9f7c13f1 Update .travis.yml 2015-03-21 04:47:21 -07:00
Alex Forencich
684f6967e5 Update .travis.yml 2015-03-21 04:40:57 -07:00
Alex Forencich
646ad2a293 Update .travis.yml 2015-03-21 04:39:27 -07:00
Alex Forencich
6bd28aa128 Update .travis.yml 2015-03-21 04:36:54 -07:00
Alex Forencich
d9c41d43f0 Update .travis.yml 2015-03-21 04:28:53 -07:00
Alex Forencich
d00471352f Update .travis.yml 2015-03-21 04:24:52 -07:00
Alex Forencich
7b991bfe0e Update AXI stream endpoint to support multiple tdata signals 2015-03-21 03:35:42 -07:00
Alex Forencich
30e597e3e0 Test with python 3 2015-03-21 03:32:42 -07:00
Alex Forencich
02a7f4d5ed Update testbenches to python 3 2015-03-21 03:32:19 -07:00
Alex Forencich
54bfdaa8c0 Cast WL to int 2015-03-21 03:19:43 -07:00