102 Commits

Author	SHA1	Message	Date
Alex Forencich	533f19dfb7	merged changes in eth	2019-10-24 12:13:08 -07:00
Alex Forencich	407c2a3a62	merged changes in pcie	2019-10-22 16:07:47 -07:00
Alex Forencich	415c2b36be	Remove old code	2019-10-19 00:38:52 -07:00
Alex Forencich	6473786a4c	Add 25G mqnic design for Alpha Data board	2019-10-18 03:26:46 -07:00
Alex Forencich	02cc2c7377	Use PCIe gen 3 x16	2019-10-17 19:02:46 -07:00
Alex Forencich	1a06f16130	Update VCU118 XDC file	2019-10-17 16:07:42 -07:00
Alex Forencich	8fa7e40507	Use new DMA subsystem	2019-10-17 16:02:14 -07:00
Alex Forencich	16c5eee499	merged changes in pcie	2019-10-17 11:46:24 -07:00
Alex Forencich	9ab0d50c0a	Add PCIe interface tuser width parameters	2019-10-05 13:56:24 -07:00
Alex Forencich	9a1a58f608	Add PCIe interface tuser width parameters	2019-10-04 16:51:07 -07:00
Alex Forencich	4a28adeded	merged changes in pcie	2019-10-04 16:29:51 -07:00
Alex Forencich	a78db05fe2	merged changes in pcie	2019-09-26 23:51:50 -07:00
Alex Forencich	89b7eccb38	Missed some changes	2019-09-26 23:51:18 -07:00
Alex Forencich	2c46513837	Update designs	2019-09-23 18:21:54 -07:00
Alex Forencich	c6e75b40a1	Don't need AXI DMA unaligned support	2019-09-23 18:11:25 -07:00
Alex Forencich	2325966973	Pull out descriptor and completion handling logic	2019-09-23 18:10:35 -07:00
Alex Forencich	6aa48f9127	Add completion op mux module	2019-09-23 14:47:09 -07:00
Alex Forencich	9219957013	Add descriptor op mux module	2019-09-23 14:47:00 -07:00
Alex Forencich	009a80aff2	Add completion write module	2019-09-23 14:44:08 -07:00
Alex Forencich	75a756e915	Add descriptor fetch module	2019-09-23 14:41:35 -07:00
Alex Forencich	835abf9412	Remove pcie_us_axi_master instances and corresponding BAR	2019-09-19 17:31:59 -07:00
Alex Forencich	b5868c8997	Update PTP perout support in VCU108 and VCU118 designs	2019-09-18 19:46:45 -07:00
Alex Forencich	2e27d6ae2f	Improve tx_scheduler_rr timing	2019-09-14 23:32:34 -07:00
Alex Forencich	bee056e7d3	Fix pipelining bug	2019-09-13 13:48:48 -07:00
Alex Forencich	132d44cd90	Increase crossbar threads count	2019-09-11 18:06:14 -07:00
Alex Forencich	5048864d86	Update tx_scheduler to handle out of order operations	2019-09-02 09:02:53 -07:00
Alex Forencich	e0a1e49d7b	Update tx_engine to return status early in case of dequeue fail	2019-09-02 08:17:09 -07:00
Alex Forencich	7f33bf4982	Update rx_engine to return length	2019-09-02 08:15:07 -07:00
Alex Forencich	ce648698ce	Enforce parameter range	2019-09-02 08:13:43 -07:00
Alex Forencich	bcfd665823	Connect queue index field in queue operation response	2019-09-01 08:29:22 -07:00
Alex Forencich	6d78315f81	Add queue index to queue operation response	2019-09-01 08:12:06 -07:00
Alex Forencich	364d835957	Split queue op tag table entry	2019-08-29 19:44:43 -07:00
Alex Forencich	ab07ab7ff7	Fix latch inference	2019-08-29 18:36:15 -07:00
Alex Forencich	d67c9ff70e	Pull out scheduler op table size parameter	2019-08-23 07:44:33 -07:00
Alex Forencich	744ac22c75	Normalize queue op table sizes	2019-08-22 19:19:51 -07:00
Alex Forencich	6a354e7aa3	Normalize descriptor table sizes	2019-08-22 19:03:19 -07:00
Alex Forencich	a4132cfda7	Integrate TX checksum offload	2019-08-22 00:45:09 -07:00
Alex Forencich	3b6bca6b93	Add transmit checksum module and testbench	2019-08-21 22:57:41 -07:00
Alex Forencich	7b2a0d5032	Sync driver model	2019-08-20 01:36:22 -07:00
Alex Forencich	e548bd0238	Initialize RAMs	2019-08-20 01:06:29 -07:00
Alex Forencich	d977cbdac2	Add feature bits	2019-08-19 23:43:52 -07:00
Alex Forencich	5f066b9fcd	Adjust ExaNIC board ID to match original PCIe ID	2019-08-19 22:04:10 -07:00
Alex Forencich	0fd9bc7376	merged changes in pcie	2019-08-19 14:32:55 -07:00
Alex Forencich	c9a17cdf90	Init scheduler queue state on reset	2019-08-13 13:51:50 -07:00
Alex Forencich	94c8dabad6	Rewrite scheduler	2019-08-13 00:45:01 -07:00
Alex Forencich	aeaabfeff5	Truncate high order address bits	2019-08-13 00:41:10 -07:00
Alex Forencich	80f06e1fcc	Update testbenches	2019-08-13 00:39:28 -07:00
Alex Forencich	d99f40db08	Add port CSRs	2019-08-13 00:27:09 -07:00
Alex Forencich	451acd3af5	Parametrize queue RAM width	2019-08-11 15:15:55 -07:00
Alex Forencich	1e06d7cca7	Clean up pipeline parameters	2019-08-11 09:55:10 -07:00