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9 Commits

Author SHA1 Message Date
Alex Forencich
53f4275ea2 Add output registers for I2C interface to improve timing 2020-10-13 23:52:52 -07:00
Alex Forencich
ac4859d88e Fix user_clk_frequency setting in testbenches 2020-10-12 23:07:43 -07:00
Alex Forencich
70b7082fb6 Implement new control registers 2020-09-19 17:25:58 -07:00
Alex Forencich
e54eb685b3 Update makefiles 2020-08-06 18:43:47 -07:00
Alex Forencich
77b9cace47 Update BAR configuration in testbenches 2020-07-28 19:01:53 -07:00
Alex Forencich
d449be8fc5 Convert to 64 bit BARs 2020-07-24 16:54:57 -07:00
Alex Forencich
f99736d4f5 Convert to TCL IP 2020-07-11 20:07:13 -07:00
Alex Forencich
50af74aa88 Change QUEUE_LOG_SIZE_WIDTH to LOG_QUEUE_SIZE_WIDTH 2020-04-20 18:43:26 -07:00
Alex Forencich
105a834790 Add mqnic design for NetFPGA SUME 2020-03-28 00:44:04 -07:00