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Author SHA1 Message Date
Alex Forencich
0dfd076f48 merged changes in eth 2021-10-13 18:22:19 -07:00
Alex Forencich
70cb88629b merged changes in axis 2021-10-13 18:17:45 -07:00
Alex Forencich
10e24cc5b1 Fix timing constraints 2021-10-13 18:07:45 -07:00
Alex Forencich
b7e8ca1311 Fix kernel module coding style 2021-10-13 16:51:32 -07:00
Alex Forencich
2c038c9b7b Update FIFO instance 2021-10-13 16:44:05 -07:00
Alex Forencich
74a7cc08e5 merged changes in eth 2021-10-13 16:41:04 -07:00
Alex Forencich
4c14289fb0 Fix instance name 2021-10-13 14:43:42 -07:00
Alex Forencich
e85deafca3 Update FIFO instance 2021-10-13 14:42:57 -07:00
Alex Forencich
1d187b9b87 merged changes in axis 2021-10-13 14:12:11 -07:00
Alex Forencich
4f1eabab17 Split async FIFO resets 2021-10-13 14:05:13 -07:00
Alex Forencich
5b49f09baa Fix kernel module coding style 2021-10-08 18:31:53 -07:00
Alex Forencich
1bce5827c9 Rework ethtool get_ts_info implementation 2021-10-08 17:47:22 -07:00
Alex Forencich
4294e5ea1d Use BIT macros 2021-10-08 16:55:56 -07:00
Alex Forencich
2fc87915e3 Update driver for i2c_board_info struct change in kernel 5.13 2021-10-05 22:20:16 -07:00
Alex Forencich
11f6522730 merged changes in pcie 2021-10-03 13:17:57 -07:00
Alex Forencich
8c5364e65a Update readme 2021-10-03 12:39:15 -07:00
Alex Forencich
cb6b15cae0 Reset error signal monitor 2021-10-03 12:17:57 -07:00
Alex Forencich
c41f0a823a Prevent latch inference 2021-10-03 11:55:27 -07:00
Alex Forencich
b2e34cd12a Byte count only needs 3 bits for single DWORD operations 2021-10-03 11:53:24 -07:00
Alex Forencich
ebac1a8be6 Derive length from op_read 2021-10-03 11:51:22 -07:00
Alex Forencich
04a80a4d35 Rework FIFO implementation for pcie_axil_master_minimal 2021-10-03 11:48:47 -07:00
Alex Forencich
85b8231abf Add IO operations to bad ops test for pcie_axil_master_minimal 2021-10-03 11:47:45 -07:00
Alex Forencich
bb74bdf2f7 Update pcie_axil_master module to support arbitrary memory operations 2021-10-03 11:46:55 -07:00
Alex Forencich
eea6b66f3f Add PCIe AXI master modules and testbenches 2021-10-02 00:59:18 -07:00
Alex Forencich
824e9fc758 Resize registers 2021-10-02 00:46:21 -07:00
Alex Forencich
c249081dd2 Use DRIVER_NAME define 2021-10-01 23:45:06 -07:00
Alex Forencich
75905778bc Use DRIVER_NAME define 2021-10-01 23:44:50 -07:00
Alex Forencich
437c69abc4 Call remove from shutdown 2021-10-01 18:25:31 -07:00
Alex Forencich
93aed3ede9 Remove UltraScale specific counters 2021-10-01 18:25:12 -07:00
Alex Forencich
4b59bad937 Print more PCIe information 2021-10-01 17:38:58 -07:00
Alex Forencich
cb52a82498 Remove MODULE_SUPPORTED_DEVICE, which was never implemented and was removed in kernel version 5.12 2021-10-01 17:35:43 -07:00
Alex Forencich
0965c77b8e Remove MODULE_SUPPORTED_DEVICE, which was never implemented and was removed in kernel version 5.12 2021-10-01 17:31:15 -07:00
Alex Forencich
aee1431e74 Remove irrelevant address computation 2021-10-01 15:56:51 -07:00
Alex Forencich
d97ac3105f Convert VCU118 to x16 2021-10-01 15:56:28 -07:00
Alex Forencich
618fdff0b8 Convert ADM_PCIE_9V3 to x16 2021-10-01 15:21:10 -07:00
Alex Forencich
adeb2c6b1c Fix alignment 2021-10-01 13:50:30 -07:00
Alex Forencich
d0705fea9b Minor optimizations to completion TLP size computation logic 2021-10-01 13:00:22 -07:00
Alex Forencich
a7b669e22f Update makefiles 2021-10-01 02:39:15 -07:00
Alex Forencich
c044898ec4 One AXI read burst per completion TLP 2021-10-01 00:20:29 -07:00
Alex Forencich
2984b5b09d Copy pcie_axil_master as pcie_axil_master_minimal 2021-09-30 22:38:28 -07:00
Alex Forencich
e0da1819c4 More tests for pipeline FIFO 2021-09-28 01:18:17 -07:00
Alex Forencich
0b5fc5b0e0 Fix off by one error 2021-09-28 01:17:57 -07:00
Alex Forencich
e48901a588 Reorganize test lists 2021-09-28 01:17:28 -07:00
Alex Forencich
d549267e17 Test async FIFO with different clock periods 2021-09-28 00:29:54 -07:00
Alex Forencich
780406197d Add 25G mqnic design for ExaNIC X25 2021-09-26 18:11:00 -07:00
Alex Forencich
92bb1bda57 Remove unused files 2021-09-26 18:00:36 -07:00
Alex Forencich
45b7e3566c Update readme 2021-09-26 01:16:34 -07:00
Alex Forencich
c8e6484af7 Use correct width for full throughput at 25G 2021-09-26 01:04:40 -07:00
Alex Forencich
f2f19f7174 Update terminology, use byte_lanes instead of byte_width 2021-09-25 22:52:19 -07:00
Alex Forencich
bc8715decc Hold read completions until pending writes complete 2021-09-25 00:46:55 -07:00