15 Commits

Author	SHA1	Message	Date
Alex Forencich	c2fea3a616	Add port register blocks with support for PHY link status reporting ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-05-04 09:03:37 -07:00
Alex Forencich	335a5e890b	Initial implementation of shared interface datapath	2021-12-31 14:33:31 -08:00
Alex Forencich	ce21774f06	Register space reorganization	2021-12-29 22:31:46 -08:00
Alex Forencich	6163efa0b8	Add output pipeline stage to descriptor FIFOs	2021-12-29 14:30:05 -08:00
Alex Forencich	7ac4797336	Add default_nettype none and resetall directives	2021-10-20 21:53:39 -07:00
Alex Forencich	607257d7bb	Fix connections	2021-10-20 20:43:11 -07:00
Alex Forencich	cef2602efe	Reorganize address space to place port registers in interface register space	2021-08-30 01:29:25 -07:00
Alex Forencich	d46cb16dbf	Add scheduler block	2021-08-30 01:28:55 -07:00
Alex Forencich	454d237ab2	Rename parameter	2021-08-30 01:27:53 -07:00
Alex Forencich	34150323df	Remove obsolete packet table size parameters	2021-08-20 18:15:06 -07:00
Alex Forencich	a19474f9dd	Use AXI lite crossbar	2021-08-11 01:31:34 -07:00
Alex Forencich	e0e34a9f0d	Update designs for PCIe module changes	2021-08-02 23:04:52 -07:00
Alex Forencich	0a7f1ccbbe	Remove string parameters	2021-06-02 18:18:23 -07:00
Alex Forencich	a3c104f7dd	Connect write done signals	2021-02-24 15:07:26 -08:00
Alex Forencich	91edbbf3dc	Rename port and interface modules	2020-11-26 15:05:59 -08:00