14 Commits

Author	SHA1	Message	Date
Alex Forencich	bd8e8e5b20	Add PTP time distribution components ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-11-07 13:07:15 -08:00
Alex Forencich	90e6dfc638	Use phase detector in PTP CDC module for coarse period tuning, use 9 LSBs of timestamp for fine sync to avoid rollover corrections, reduce FNS comparison width to 4 bits ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-09-23 14:58:44 -07:00
Alex Forencich	5a37442706	Merge FNS registers into NS registers in PTP CDC module ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-09-22 22:52:59 -07:00
Alex Forencich	cf441f004d	Rename source sync signals in PTP CDC module for consistency ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-09-22 01:07:12 -07:00
Alex Forencich	a443e8862c	Update TCL timing constraints to handle clocks from OOC IP that are not constrained during synthesis ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-07-26 14:59:19 -07:00
Alex Forencich	70cc19ff15	Add MAC control layer to core 1G and 10G MAC modules ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-07-23 22:24:42 -07:00
Alex Forencich	274831c268	Fix PTP clock CDC module timing constraints ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-05-05 21:41:41 -07:00
Alex Forencich	40265a3e1c	Add timing constraints for Quartus Prime Pro	2021-05-18 18:30:33 -07:00
Alex Forencich	7751aba8da	Reorganize timing constraints	2021-05-18 16:15:41 -07:00
Alex Forencich	31c7349f90	Rewrite PTP clock CDC module for improved performance and timing closure at 25G	2021-03-30 15:57:46 -07:00
Alex Forencich	59a51b4a9f	Add SDC constraints for Quartus	2020-07-10 14:14:02 -07:00
Alex Forencich	77bae7a77e	Add PTP clock CDC module and testbench	2019-07-15 15:16:17 -07:00
Alex Forencich	8e2d936884	Add MII PHY interface, MAC wrappers, and testbenches	2019-03-28 19:18:03 -07:00
Alex Forencich	58201866f3	Add timing constraints	2019-03-28 17:53:51 -07:00