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Author SHA1 Message Date
Alex Forencich
ef2f01bd9f Update XDC 2020-09-23 14:24:42 -07:00
Alex Forencich
4ae9ec818c Add timing constraints for LED driver 2020-09-22 22:13:54 -07:00
Alex Forencich
c7594c77ab Add fb2CG AXI example design 2020-09-20 01:17:52 -07:00
Alex Forencich
722222a01c Add AU250 AXI example design 2020-09-18 14:51:35 -07:00
Alex Forencich
0080f631c6 Add AU200 AXI example design 2020-09-18 14:51:24 -07:00
Alex Forencich
d7f96eb104 Rewrite priority encoder to remove recusive construction 2020-08-17 18:30:40 -07:00
Alex Forencich
fed4c93b9c Update XDC 2020-08-06 22:06:16 -07:00
Alex Forencich
1e75c3cc70 Fix AXI stream DMA client bug causing dropped writes when widths are the same 2020-08-06 21:32:10 -07:00
Alex Forencich
0d4e9989c8 Fix asserts 2020-08-06 21:31:58 -07:00
Alex Forencich
963f4f8555 Add ZCU106 AXI example design 2020-08-06 18:25:34 -07:00
Alex Forencich
b79ddf5ebd Update makefiles 2020-08-06 18:22:30 -07:00
Alex Forencich
8045992eb6 Remove extraneous code 2020-07-27 22:29:04 -07:00
Alex Forencich
1f523f0bb4 Remove unused reg 2020-07-26 21:39:10 -07:00
Alex Forencich
dd97d2d749 Minor refactoring 2020-07-25 22:09:30 -07:00
Alex Forencich
dc48d86b99 Improve BAR initialization 2020-07-24 22:54:55 -07:00
Alex Forencich
65fd5ef947 Fix AU50 XDC file 2020-07-23 22:36:00 -07:00
Alex Forencich
56dbcb8274 Add AU50 AXI example design 2020-07-17 00:04:13 -07:00
Alex Forencich
d3a1c903d3 XDC clean up 2020-07-13 23:58:45 -07:00
Alex Forencich
5dbb771958 Add AU280 AXI example design 2020-07-12 11:42:48 -07:00
Alex Forencich
ebae4e436d Update AXI simulation model 2020-07-02 21:28:35 -07:00
Alex Forencich
281e1a2156 Convert to TCL IP 2020-07-01 23:53:58 -07:00
Alex Forencich
d6ad22d435 Add DMA block diagram 2020-05-07 12:36:37 -07:00
Alex Forencich
6e974aca27 Driver update for Linux kernel API change 2020-03-26 16:12:56 -07:00
Alex Forencich
566dfa07e7 Read DMA timing optimizations 2020-03-26 14:34:48 -07:00
Alex Forencich
08d92fd138 Add pipeline stage for memory write generation to improve completion handling throughput 2020-03-24 21:58:48 -07:00
Alex Forencich
f8ce39c585 Timing optimization 2020-03-24 19:41:02 -07:00
Alex Forencich
060320010d Don't configure MSI if already configured 2020-03-02 21:16:09 -08:00
Alex Forencich
37934485af Timing optimization for ram_wrap computation 2020-02-28 13:22:35 -08:00
Alex Forencich
983610d6d9 Timing optimization for mask computation 2020-02-28 13:02:26 -08:00
Alex Forencich
50124ce66d Timing optimization 2020-02-28 01:01:37 -08:00
Alex Forencich
db4d0a8f94 Timing optimizations 2020-02-27 20:00:37 -08:00
Alex Forencich
092c72ba66 Compute req_last_tlp in advance 2020-02-27 18:19:45 -08:00
Alex Forencich
18bf537f4f Fix register size 2020-02-27 15:47:18 -08:00
Alex Forencich
a00589e5a3 Timing optimizations 2020-02-27 15:24:24 -08:00
Alex Forencich
bd0482fc96 Update script for sysfs changes 2020-02-26 12:21:36 -08:00
Alex Forencich
8d087ecc92 Consolidate example driver code 2020-02-13 13:16:05 -08:00
Alex Forencich
ec2ceb8e56 Timing optimizations 2020-01-24 13:51:30 -08:00
Alex Forencich
3bad28d626 Add VCU1525 AXI example design 2020-01-15 22:43:33 -08:00
Alex Forencich
e14f6c6f0e Remove unused signals 2019-12-13 15:33:12 -08:00
Alex Forencich
dfd9744b3e PCIe DMA write bandwidth optimizations 2019-12-13 15:31:37 -08:00
Alex Forencich
a6d64bbcbb Remove extraneous character 2019-12-07 14:36:32 -08:00
Alex Forencich
d561195dc8 Add get_data_credits to TLP 2019-12-07 00:54:16 -08:00
Alex Forencich
7567db1818 Add credit-based flow control to DMA cores 2019-12-06 23:24:36 -08:00
Alex Forencich
00858212c6 Placeholder values for flow control credit outputs 2019-12-06 19:16:05 -08:00
Alex Forencich
60a2813fbc Fix indentation 2019-12-05 22:09:04 -08:00
Alex Forencich
f3a6cec13a Use nonblocking assign 2019-12-03 15:47:58 -08:00
Alex Forencich
8985c6dbf3 Add RQ sequence number inputs, operation table, TX_LIMIT parameter to ultrascale write DMA modules 2019-12-03 15:46:36 -08:00
Alex Forencich
a1d0fb810f Reorganize 2019-12-02 15:27:27 -08:00
Alex Forencich
2afef8c6d8 Fix use before define 2019-12-02 15:18:08 -08:00
Alex Forencich
80dafd5870 Check FIFO depth 2019-12-02 15:15:24 -08:00