FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00
Code Issues Projects Releases Wiki Activity
2,732 Commits 1 Branch 0 Tags
Commit Graph

7 Commits

Author SHA1 Message Date
Alex Forencich
ed2d34153d Use PHY rx_status signal for link status detection 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-17 00:46:05 -07:00
Alex Forencich
835f0d38f0 Update PTP subsystem to use separate clock for improved stability 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-06 17:46:16 -07:00
Alex Forencich
c2fea3a616 Add port register blocks with support for PHY link status reporting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-04 09:03:37 -07:00
Alex Forencich
e91de95955 Fix rb_drp timing constraint for write enable signal 2022-03-02 17:31:17 -08:00
Alex Forencich
90d28ec9a2 Add common 10G PHY + GTH/GTY transceiver wrapper module 2022-03-02 17:28:40 -08:00
Alex Forencich
614b391c48 Add DRP register block 2022-02-21 23:20:54 -08:00
Alex Forencich
15cb21dbd1 Reorganize timing constraints 2021-05-20 15:24:01 -07:00