FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity
1,050 Commits 1 Branch 0 Tags
Commit Graph

30 Commits

Author SHA1 Message Date
Alex Forencich
8e60adf567 Update axis_switch instances 2021-11-29 14:43:01 -08:00
Alex Forencich
74f32c6a59 Add missing PHY instance ports 2021-11-02 20:28:26 -07:00
Alex Forencich
6b18e56cb1 Add default_nettype none and resetall directives 2021-10-20 17:29:12 -07:00
Alex Forencich
cf016dc4ee Rework GT instances in VCU108 design 2021-10-19 22:11:34 -07:00
Alex Forencich
5415c41c41 Remove string parameters 2021-06-02 17:50:26 -07:00
Alex Forencich
2a2d8ac966 Fix reg type in VCU108 and VCU118 example designs 2020-12-20 14:22:52 -08:00
Alex Forencich
fd908dd2aa Clean up clock connections 2020-08-06 17:15:38 -07:00
Alex Forencich
a27c04a949 Convert to TCL IP 2020-07-01 19:43:26 -07:00
Alex Forencich
27ed447005 Use common sync_reset module files 2020-03-27 18:27:45 -07:00
Alex Forencich
a55c354924 Parametrize Ethernet frame parsing 2020-02-21 21:37:57 -08:00
Alex Forencich
c5e886769a Fix typo 2019-07-19 10:29:55 -07:00
Alex Forencich
16e5ec2106 Update example designs 2019-07-18 17:13:47 -07:00
Alex Forencich
27999924a0 Update VCU108 example designs 2019-06-15 17:35:49 -07:00
Alex Forencich
5428d81fd6 Update AXI stream switch instances 2019-03-28 23:56:06 -07:00
Alex Forencich
e120a85607 Use correct clock 2019-03-28 17:56:55 -07:00
Alex Forencich
0a6bee6d69 Update example designs 2018-11-08 09:17:29 -08:00
Alex Forencich
7d6889add6 Update example designs 2018-10-30 21:32:32 -07:00
Alex Forencich
8982b4f4e1 Fix modsell pin 2018-06-29 13:00:41 -07:00
Alex Forencich
cd51821bf7 Add parameters 2018-06-22 18:56:05 -07:00
Alex Forencich
298ae4defa Update MAC module instantiation 2018-06-13 22:16:02 -07:00
Alex Forencich
855b593ce5 Minor updates to 10G example designs 2018-05-31 16:05:41 -07:00
Alex Forencich
0fd157964a Happy new year 2018-02-26 12:50:51 -08:00
Alex Forencich
bd27156f35 AXI stream updates 2018-02-26 00:08:08 -08:00
Alex Forencich
69253d2d83 Update VCU108 example design 2017-06-01 06:48:50 -07:00
Alex Forencich
9b2ac9dfc1 Happy new year 2017-05-18 13:47:45 -07:00
Alex Forencich
270641b7a3 Update UDP modules and example designs to utilize UDP checksum modules 2016-09-30 22:15:21 -07:00
Alex Forencich
36af29db77 Add i2c init code for si570 reference oscillator 2016-08-03 14:44:10 -04:00
Alex Forencich
833d1dac81 Route 10G link status to LEDs 2016-07-28 09:57:36 -04:00
Alex Forencich
2365f4b6fc Connect QSFP module control pins 2016-07-28 09:56:13 -04:00
Alex Forencich
795ae8a4db Add 10G example design for VCU108 board 2016-07-26 14:14:16 -04:00