20 Commits

Author	SHA1	Message	Date
Alex Forencich	9dafc3aaee	Use internal BYTE_LANES parameter ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-07-06 16:28:08 -07:00
Alex Forencich	f705646e3e	Pull out header size as a parameter ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-06-29 15:48:39 -07:00
Alex Forencich	609aac39a0	Rewrite early ready condition ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-05-15 17:47:30 -07:00
Alex Forencich	9b5a8cf24a	Rewrite resets ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-05-15 17:39:44 -07:00
Alex Forencich	853c1737aa	Simplify logic	2021-12-31 22:57:11 -08:00
Alex Forencich	6b18e56cb1	Add default_nettype none and resetall directives	2021-10-20 17:29:12 -07:00
Alex Forencich	a55c354924	Parametrize Ethernet frame parsing	2020-02-21 21:37:57 -08:00
Alex Forencich	d2fedc4134	Rename ports	2018-11-07 22:35:06 -08:00
Alex Forencich	0fd157964a	Happy new year	2018-02-26 12:50:51 -08:00
Alex Forencich	9b2ac9dfc1	Happy new year	2017-05-18 13:47:45 -07:00
Alex Forencich	9c01e114b4	Happy new year	2016-01-05 00:34:32 -08:00
Alex Forencich	a98dfce099	Update output registers, remove extraneous resets, fix constant widths	2015-11-09 23:50:34 -08:00
Alex Forencich	cc5fead04d	Convert to synchronous resets	2015-10-09 22:36:58 -07:00
Alex Forencich	51b5335318	Remove z from default states for FSM inference	2015-03-09 02:38:39 -07:00
Alex Forencich	0e26b3a8a4	Put back lane shifting logic	2014-10-28 00:54:15 -07:00
Alex Forencich	205be7ed27	Rework AXI ethernet modules to separate output register	2014-10-23 00:05:06 -07:00
Alex Forencich	d7f30a777b	Update comments	2014-09-15 19:05:18 -07:00
Alex Forencich	a8958f4b23	Remove unnecessary registers	2014-09-15 19:04:49 -07:00
Alex Forencich	46c29160ff	Wait for header instead of payload	2014-09-15 19:03:31 -07:00
Alex Forencich	8e4d162667	Add ethernet frame to AXI stream modules	2014-09-14 01:06:48 -07:00