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Author SHA1 Message Date
Alex Forencich
59911c5ba7 fpga/mqnic/Nexus_K3P_S: Switch Cisco Nexus K3P-S designs to use 10 MHz TCXO for PTP reference clock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 14:33:32 -08:00
Alex Forencich
a0aa614362 fpga/mqnic/Nexus_K3P_Q: Switch Cisco Nexus K3P-Q designs to use 10 MHz TCXO for PTP reference clock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 14:33:00 -08:00
Alex Forencich
4b7d51133f fpga/mqnic: Enable statistics counters on all targets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 13:06:39 -08:00
Alex Forencich
e8aaadd102 fpga: Clean up top-level PCIe interface parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-04 23:56:56 -08:00
Alex Forencich
08f49d7e17 fpga/mqnic: Add missing DRP frequency parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-04 22:07:58 -08:00
Alex Forencich
3a7343ec6d fpga/mqnic: Add missing connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-04 22:03:21 -08:00
Alex Forencich
0644a12a48 fpga/mqnic: Remove extraneous top-level parameter RX_RSS_ENABLE from config.tcl scripts 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-03 21:32:51 -08:00
Alex Forencich
347a03b347 fpga/mqnic: Rework PCIe IP core configuration, fixes disrupted MSI-X settings with application section enabled and issues with PCIe class code on 7-series and UltraScale 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-03 18:16:12 -08:00
Alex Forencich
c5003d0c6d fpga/mqnic: Select advanced mode for Xilinx PCIe IP core config to access MSI-X settings 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-03 15:35:16 -08:00
Alex Forencich
ad18c19da9 fpga/mqnic: Fix default class code for UltraScale and 7-series devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-03 15:33:52 -08:00
Alex Forencich
5d1df56706 fpga/app/dma_bench: Update counter labels 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-03 15:29:58 -08:00
Alex Forencich
78363dd2d8 fpga/mqnic/AU280: Add DMA bench target for Alveo U280 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-01 17:52:17 -08:00
Alex Forencich
0e6c48f468 fpga/mqnic/AU50: Add DMA bench target for Alveo U50 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-01 17:51:44 -08:00
Alex Forencich
a4e115949b fpga/mqnic/AU250: Add DMA bench target for Alveo U250 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-01 17:51:31 -08:00
Alex Forencich
2eafa56c75 fpga/mqnic/AU200: Add DMA bench target for Alveo U200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-01 17:51:16 -08:00
Alex Forencich
6d4373ec97 fpga/common: Rework stats counter to use pipeline and infer URAM 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-01 17:15:56 -08:00
Alex Forencich
bee1703199 fpga/app/dma_bench: Refactor DMA benchmark application, use register blocks 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-30 23:26:05 -08:00
Alex Forencich
bdf05cfaf3 fpga/app/dma_bench: Use cycle count conversion methods 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-24 01:43:06 -08:00
Alex Forencich
dc50705d01 lib/mqnic: Added helper methods for converting cycle counts to/from time 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-24 01:41:51 -08:00
Alex Forencich
66f305c46c modules/mqnic: Added helper methods for converting cycle counts to/from time 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-24 01:41:31 -08:00
Alex Forencich
48ae81e3fb fpga/app/dma_bench: Use mqnic_stats_read to read counters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-23 18:02:31 -08:00
Alex Forencich
979b7b6030 modules/mqnic: Add statistics counter read support to mqnic kernel module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-23 17:49:38 -08:00
Alex Forencich
051dca3601 modules/mqnic: Add clock info support to mqnic kernel module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-23 17:49:14 -08:00
Alex Forencich
6cfd808823 utils: Dump statistics counters in mqnic-dump 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-23 17:38:28 -08:00
Alex Forencich
ede33bb23e lib/mqnic: Add statistics counter read support to userspace library 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-23 17:38:18 -08:00
Alex Forencich
3daeb18d5f lib/mqnic: Refactor clock info register block code in userspace library 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-23 17:37:45 -08:00
Alex Forencich
61caf147f7 Use CMAC wrapper in 100G mqnic design for XUP-P3R 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 18:26:10 -08:00
Alex Forencich
596db2d756 Use CMAC wrapper in 100G mqnic design for VCU118 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 18:24:43 -08:00
Alex Forencich
db621ffa7d Use CMAC wrapper in 100G mqnic design for 250-SoC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 18:01:43 -08:00
Alex Forencich
cdda035427 Use CMAC wrapper in 100G mqnic design for VCU1525 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 17:35:09 -08:00
Alex Forencich
e51e5a84af Use CMAC wrapper in 100G mqnic design for Alveo U50 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 17:07:12 -08:00
Alex Forencich
39c5744e99 Use CMAC wrapper in 100G mqnic design for Alveo U280 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 16:30:55 -08:00
Alex Forencich
3d993e4479 Use CMAC wrapper in 100G mqnic design for Alveo U250 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 16:00:45 -08:00
Alex Forencich
f67bd98719 Use CMAC wrapper in 100G mqnic design for Alveo U200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 12:38:14 -08:00
Alex Forencich
49be896333 Use CMAC wrapper in 100G mqnic design for ADM-PCIE-9V3 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 11:49:34 -08:00
Alex Forencich
f70f4d9b90 Use CMAC wrapper in 100G mqnic design for fb2CG@KU15P 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 11:42:07 -08:00
Alex Forencich
bf7cf3fef9 Add CMAC wrapper 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-09 20:58:30 -08:00
Alex Forencich
f6262c3606 fpga/mqnic: Update FIFO parameter naming 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 23:57:50 -07:00
Alex Forencich
0cb106e2aa merged changes in eth 2022-11-01 23:57:35 -07:00
Alex Forencich
2199a15c75 Force possible floating point parameter value to integer when taking clog2 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 23:56:27 -07:00
Alex Forencich
5e528e0057 Update FIFO PIPELINE_OUTPUT to RAM_PIPELINE 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 23:56:11 -07:00
Alex Forencich
b765c78f56 merged changes in axis 2022-11-01 23:55:36 -07:00
Alex Forencich
ed6130575d Update async FIFO timing constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 23:27:39 -07:00
Alex Forencich
9c3409f9d7 Add option for output FIFO to improve pipelining and RAM inference for large FIFOs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 19:02:53 -07:00
Alex Forencich
d4cf84ccf0 Consolidated RAM pipeline output wires 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 16:36:11 -07:00
Alex Forencich
6f761bc4a5 Use separate RAM output register for better pipeline register inference 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 14:46:24 -07:00
Alex Forencich
a0f46801a1 Replace OUTPUT_PIPELINE with RAM_PIPELINE 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 14:40:58 -07:00
Alex Forencich
fa4e8e70cb Add intermediate signal for end of FIFO RAM pipeline 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 14:03:51 -07:00
Alex Forencich
e542d39a75 Fix assignment type 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-20 09:21:34 -07:00
Alex Forencich
8c733dff9e fpga/mqnic/fb2CG: Update placement constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-17 13:01:16 -07:00