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Author SHA1 Message Date
Alex Forencich
5ad725bd0f added axi as a subproject 
git-subtree-dir: fpga/lib/axi
git-subtree-mainline: d644d8c5e30c9b704704d8974ee73f1573ac2af2
git-subtree-split: 23a14dc5dfa1d18c0c1e73ff00bf462d1b7ea5da
 2019-07-15 14:55:51 -07:00
Alex Forencich
d644d8c5e3 Add axis symlink 2019-07-15 14:55:44 -07:00
Alex Forencich
de181120b8 added eth as a subproject 
git-subtree-dir: fpga/lib/eth
git-subtree-mainline: 4cdce8caa74728a4973261dae0e00fcd479af9ac
git-subtree-split: e5171d874916b3e23a02d5621e91dd9ff02b7fcb
 2019-07-15 14:55:25 -07:00
Alex Forencich
4cdce8caa7 Add subtree scripts 2019-07-15 14:55:10 -07:00
Alex Forencich
dce357bfed Initial commit 2019-07-15 14:53:31 -07:00
Alex Forencich
23a14dc5df Update readme 2019-07-09 00:18:58 -07:00
Alex Forencich
21dbe318b4 Add AXI lite clock domain crossing module, testbench, and timing constraints 2019-07-09 00:18:27 -07:00
Alex Forencich
36523dd7cc Fix typo 2019-07-08 17:57:47 -07:00
Alex Forencich
f924f75b70 Use computed word size 2019-07-08 17:57:30 -07:00
Alex Forencich
7591cb4d1c Update readme 2019-07-08 17:53:39 -07:00
Alex Forencich
ed344f352f Add AXI to AXI lite adapter modules and testbenches 2019-07-08 17:51:12 -07:00
Alex Forencich
f5830b6407 Backpressure updates 2019-07-08 17:34:09 -07:00
Alex Forencich
abcb20612e Remove redundant code 2019-07-08 00:28:27 -07:00
Alex Forencich
1bd22f5208 Ensure rready clear when returning to idle 2019-07-05 23:29:39 -07:00
Alex Forencich
3f21db4584 bresp handling update 2019-07-04 14:23:37 -07:00
Alex Forencich
e5171d8749 Enable flash programming in VCU118 example designs 2019-07-01 17:51:31 -07:00
Alex Forencich
fdfb517761 Add PTP perout module and testbench 2019-06-27 01:30:18 -07:00
Alex Forencich
386ff91210 Add ExaNIC X10 flash programming commands 2019-06-27 01:27:32 -07:00
Alex Forencich
d62a5ad050 Fix quotes 2019-06-27 01:26:58 -07:00
Alex Forencich
dfafa9c83d Update vivado.mk 2019-06-27 00:59:36 -07:00
Alex Forencich
025f05e667 Add nojournal and nolog 2019-06-27 00:48:20 -07:00
Alex Forencich
af4f675840 Fix for dash 2019-06-27 00:15:36 -07:00
Alex Forencich
cfcd9da375 Update IP 2019-06-26 20:50:05 -07:00
Alex Forencich
15b3aaf2e7 Update programming commands 2019-06-26 20:17:45 -07:00
Alex Forencich
963a8f7459 Add flash ADM-PCIE-9V3 flash programming commands 2019-06-26 20:06:22 -07:00
Alex Forencich
88cc4e6e24 Update VCU108 flash programming commands 2019-06-26 19:50:28 -07:00
Alex Forencich
dc4416a261 Update Arty flash programming commands 2019-06-26 19:00:20 -07:00
Alex Forencich
d166350d77 Update Arty XDC 2019-06-26 18:59:41 -07:00
Alex Forencich
7fd0f79f81 Remove extraneous parameter 2019-06-26 12:26:55 -07:00
Alex Forencich
daf1d3106f Enable flash programming on VCU108 2019-06-26 01:28:54 -07:00
Alex Forencich
7cce7896b5 Update programming commands 2019-06-25 23:46:44 -07:00
Alex Forencich
94a3be6e1d Fix possible backpressure issue 2019-06-22 12:47:52 -07:00
Alex Forencich
f6acefbf94 Simplify logic 2019-06-22 01:51:06 -07:00
Alex Forencich
ebbaea908b Add strb_offset_mask_reg 2019-06-22 00:13:11 -07:00
Alex Forencich
b1edaf1ae4 Optimize check 2019-06-22 00:05:15 -07:00
Alex Forencich
6ed937d521 Add zero offset reg 2019-06-21 20:42:20 -07:00
Alex Forencich
967aa8c2f3 Mask instead of barrel shift 2019-06-21 20:38:09 -07:00
Alex Forencich
435f0b8749 Timing optimization of wstrb 2019-06-21 12:04:58 -07:00
Alex Forencich
df04d7e68d CRC handling logic optimizations 2019-06-20 18:10:53 -07:00
Alex Forencich
9e7f4a9836 Remove unused state bit 2019-06-20 18:02:15 -07:00
Alex Forencich
0927f4c326 Fix readme 2019-06-19 23:51:04 -07:00
Alex Forencich
4410d74848 Update readme 2019-06-19 23:28:15 -07:00
Alex Forencich
1eb9c39ed3 Add VCU118 25G example design 2019-06-19 23:25:06 -07:00
Alex Forencich
1a28b0bf67 Add ADM-PCIE-9V3 25G example design 2019-06-19 23:22:56 -07:00
Alex Forencich
a031993b26 Update example designs 2019-06-19 23:16:57 -07:00
Alex Forencich
eb1f38a749 More critical path optimizations 2019-06-19 15:06:55 -07:00
Alex Forencich
134ce04777 Add configurable serdes pipeline register chain 2019-06-19 00:57:28 -07:00
Alex Forencich
3ba91ce091 Wait for block lock 2019-06-19 00:53:41 -07:00
Alex Forencich
303dec8165 Sum errors across data and header 2019-06-19 00:25:41 -07:00
Alex Forencich
1d3554c37e Rework pointer handling to improve timing 2019-06-16 23:53:26 -07:00