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8 Commits

Author SHA1 Message Date
Alex Forencich
c2fea3a616 Add port register blocks with support for PHY link status reporting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-04 09:03:37 -07:00
Alex Forencich
f67c704b11 Update placement constraints for hierarchy changes 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-02 13:16:20 -07:00
Alex Forencich
47f0044099 fpga/mqnic: Fix incorrect SLR in placement constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-14 11:51:10 -07:00
Alex Forencich
6f197c7cb4 Add PHY instances to Ethernet pblocks 2022-03-24 21:30:55 -07:00
Alex Forencich
0e15a7a16b Avoid critical warning from placement constraints when configured with a single interface 2022-03-17 15:39:13 -07:00
Alex Forencich
0928f56a45 Add Ethernet interface placement constraints for VCU118 2022-03-17 00:48:44 -07:00
Alex Forencich
25421b8994 Update placement constraints 2022-03-15 15:28:43 -07:00
Alex Forencich
39691759aa Unified 10G/25G design for VCU118 2022-03-14 21:40:29 -07:00