Alex Forencich
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5dc38f11b7
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Use unified 10G/25G design for Alveo VCU1525
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-13 20:42:40 -07:00 |
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Alex Forencich
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a221adc468
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Use unified 10G/25G design for Alveo U50
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-13 20:40:38 -07:00 |
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Alex Forencich
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147435dfe1
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Use unified 10G/25G design for Alveo U280
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-13 20:38:34 -07:00 |
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Alex Forencich
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ea80d853ed
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Use unified 10G/25G design for Alveo U250
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-13 19:53:21 -07:00 |
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Alex Forencich
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0b18633bb1
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Use unified 10G/25G design for Alveo U200
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-13 19:49:25 -07:00 |
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Alex Forencich
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489ee73355
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Use unified 10G/25G design for VCU118
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-13 19:02:57 -07:00 |
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Alex Forencich
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729c5a61ce
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Use unified 10G/25G design for ADM-PCIE-9V3
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-13 18:59:33 -07:00 |
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Alex Forencich
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48cbe43fa7
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Update Vivado makefiles
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-13 18:48:34 -07:00 |
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Alex Forencich
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b6a9092a9f
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Update makefiles for Intel devices
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-13 17:46:34 -07:00 |
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Alex Forencich
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c4376c8674
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Update XDC files
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-13 17:12:32 -07:00 |
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Alex Forencich
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c65161e696
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Remove recursively-expanded macros for module parameters in makefiles
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-02-17 16:04:16 -08:00 |
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Alex Forencich
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57803eeeb8
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Remove deprecated assignments
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-01-24 15:07:45 -08:00 |
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Alex Forencich
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7a0e88ffea
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Update vivado.mk
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2023-01-13 14:57:46 -08:00 |
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Alex Forencich
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f3d5e74527
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Add RV901T example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-01-01 22:03:14 -08:00 |
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Alex Forencich
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8c3df76b97
|
Fix signal name
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-12-27 18:26:58 -08:00 |
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Alex Forencich
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1f80696b55
|
Use start_soon instead of fork
|
2021-12-10 18:19:11 -08:00 |
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Alex Forencich
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8e60adf567
|
Update axis_switch instances
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2021-11-29 14:43:01 -08:00 |
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Alex Forencich
|
d052264659
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Add 520N-MX 10G example design
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2021-11-03 00:48:06 -07:00 |
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Alex Forencich
|
9e44987f60
|
Reorganize PHY instances
|
2021-11-02 23:30:48 -07:00 |
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Alex Forencich
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728e86c554
|
Update QSF/SDC files
|
2021-11-02 23:30:06 -07:00 |
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Alex Forencich
|
74f32c6a59
|
Add missing PHY instance ports
|
2021-11-02 20:28:26 -07:00 |
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Alex Forencich
|
6b18e56cb1
|
Add default_nettype none and resetall directives
|
2021-10-20 17:29:12 -07:00 |
|
Alex Forencich
|
9ff4454db0
|
Update makefiles
|
2021-10-20 17:21:58 -07:00 |
|
Alex Forencich
|
0f2478d68c
|
Fix wires
|
2021-10-20 17:21:16 -07:00 |
|
Alex Forencich
|
9f6f388a3c
|
Rework GT instances in HTG9200 design
|
2021-10-20 00:57:11 -07:00 |
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Alex Forencich
|
527c2f1b89
|
Rework GT instances in fb2CG@KU15P design
|
2021-10-20 00:56:13 -07:00 |
|
Alex Forencich
|
05770c5a1b
|
Rework GT instances in VCU118 designs
|
2021-10-19 22:13:02 -07:00 |
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Alex Forencich
|
531f751e67
|
Update VCU118 XDC
|
2021-10-19 22:11:56 -07:00 |
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Alex Forencich
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cf016dc4ee
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Rework GT instances in VCU108 design
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2021-10-19 22:11:34 -07:00 |
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Alex Forencich
|
1f76eb4534
|
Update VCU108 XDC
|
2021-10-19 22:10:32 -07:00 |
|
Alex Forencich
|
a1da0ba184
|
Rework GT instances in VCU1525 design
|
2021-10-19 18:40:32 -07:00 |
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Alex Forencich
|
0b41dc4011
|
Rework GT instances in ZCU102 design
|
2021-10-19 18:38:22 -07:00 |
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Alex Forencich
|
e3f8879474
|
Rework GT instances in ZCU106 design
|
2021-10-19 18:30:35 -07:00 |
|
Alex Forencich
|
4ce218bc5d
|
Rework GT instances in ADM-PCIE-9V3 designs
|
2021-10-19 18:29:18 -07:00 |
|
Alex Forencich
|
21da6f58dc
|
Rework GT instances in Alveo U280 design
|
2021-10-19 18:28:10 -07:00 |
|
Alex Forencich
|
4fdc6408bc
|
Rework GT instances in Alveo U50 design
|
2021-10-19 18:14:50 -07:00 |
|
Alex Forencich
|
cc4256666a
|
Rework GT instances in Alveo U250 design
|
2021-10-19 17:47:15 -07:00 |
|
Alex Forencich
|
f11f7ecac9
|
Rework GT instances in Alveo U200 design
|
2021-10-19 17:45:43 -07:00 |
|
Alex Forencich
|
38e3244caa
|
Rework GT instances in ExaNIC X10 design
|
2021-10-18 00:34:06 -07:00 |
|
Alex Forencich
|
fa77fe54f3
|
Rework GT instances in ExaNIC X25 design
|
2021-10-18 00:32:37 -07:00 |
|
Alex Forencich
|
4aa672f8f3
|
Update example designs
|
2021-10-17 20:20:26 -07:00 |
|
Alex Forencich
|
4c14289fb0
|
Fix instance name
|
2021-10-13 14:43:42 -07:00 |
|
Alex Forencich
|
e85deafca3
|
Update FIFO instance
|
2021-10-13 14:42:57 -07:00 |
|
Alex Forencich
|
29313d5e02
|
Add HTG-9200 10G example design
|
2021-07-08 11:58:04 -07:00 |
|
Alex Forencich
|
97182ccf4e
|
Update vivado.mk
|
2021-06-23 20:07:29 -07:00 |
|
Alex Forencich
|
5415c41c41
|
Remove string parameters
|
2021-06-02 17:50:26 -07:00 |
|
Alex Forencich
|
b09e01ba48
|
Update S10MX SDC
|
2021-05-19 21:57:48 -07:00 |
|
Alex Forencich
|
cee82cb695
|
Add Stratix 10 DX 10G example design
|
2021-05-19 21:00:54 -07:00 |
|
Alex Forencich
|
13c1bbe79a
|
Update S10MX QSF
|
2021-05-19 16:48:58 -07:00 |
|
Alex Forencich
|
bf6fddd1db
|
Add Stratix 10 MX 10G example design
|
2021-05-18 19:16:30 -07:00 |
|