22 Commits

Author	SHA1	Message	Date
Alex Forencich	5e528e0057	Update FIFO PIPELINE_OUTPUT to RAM_PIPELINE ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-11-01 23:56:11 -07:00
Alex Forencich	6b18e56cb1	Add default_nettype none and resetall directives	2021-10-20 17:29:12 -07:00
Alex Forencich	77938fa422	Update MAC modules for changes in FIFO modules	2021-08-26 00:55:12 -07:00
Alex Forencich	909ccae151	Properly synchronize bad FCS status output	2020-12-01 14:01:15 -08:00
Alex Forencich	8d909a082f	Fix MAC FIFO parameters	2020-04-06 21:15:17 -07:00
Alex Forencich	3bd7be44fa	Update FIFO instances and update MACs to use combined FIFO adapter module	2019-07-18 16:25:49 -07:00
Alex Forencich	8285f94eaa	Rename tx_sync regs	2019-03-28 16:27:33 -07:00
Alex Forencich	3eaed305f5	Connect TX underflow status outputs	2019-03-28 16:27:15 -07:00
Alex Forencich	585ccefa15	Add TX underflow error signal	2019-03-26 12:42:08 -07:00
Alex Forencich	ad8828d5b7	Update FIFO instances	2018-10-30 11:58:06 -07:00
Alex Forencich	fea477db09	Add unused ports	2018-06-11 16:36:44 -07:00
Alex Forencich	0fd157964a	Happy new year	2018-02-26 12:50:51 -08:00
Alex Forencich	bd27156f35	AXI stream updates	2018-02-26 00:08:08 -08:00
Alex Forencich	8ff4312601	Update MAC modules to use new modules	2017-05-31 18:37:33 -07:00
Alex Forencich	9b2ac9dfc1	Happy new year	2017-05-18 13:47:45 -07:00
Alex Forencich	9c01e114b4	Happy new year	2016-01-05 00:34:32 -08:00
Alex Forencich	a98dfce099	Update output registers, remove extraneous resets, fix constant widths	2015-11-09 23:50:34 -08:00
Alex Forencich	08afe3a5d2	Synchronize MAC status signals	2015-10-09 22:51:55 -07:00
Alex Forencich	55071645fd	Update async FIFO instances	2015-10-09 22:35:25 -07:00
Alex Forencich	ec95a6055d	Feed through and synchronize FIFO status signals	2015-05-12 19:12:23 -07:00
Alex Forencich	16fec34ddc	Default FIFO size at least 2 MTU (3000 bytes)	2015-05-08 01:44:55 -07:00
Alex Forencich	73bebaba46	Add FIFO wrapper for gigabit MAC module	2015-05-07 23:45:30 -07:00