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Author SHA1 Message Date
Alex Forencich
39200d84cb Update simulation models to support 512 bit interface 2019-10-14 15:45:41 -07:00
Alex Forencich
89ff925545 Timing optimizations 2019-10-14 14:00:55 -07:00
Alex Forencich
e96ee85356 Update example designs 2019-10-13 17:16:01 -07:00
Alex Forencich
2c43a6e189 Use mmap objects instead of bytearrays 2019-10-13 15:41:12 -07:00
Alex Forencich
75563c65f0 Add DMA interface mux modules 2019-10-12 23:08:21 -07:00
Alex Forencich
fdd7faef4f Add Xilinx Ultrascale PCIe DMA interface modules and testbenches 2019-10-12 23:03:42 -07:00
Alex Forencich
25de311347 Add DMA RAM module 2019-10-12 22:48:23 -07:00
Alex Forencich
e1035ed57d Add AXI stream sink DMA client module and testbench 2019-10-12 22:35:57 -07:00
Alex Forencich
baeeb8ea5c Add AXI stream source DMA client module and testbench 2019-10-12 22:34:15 -07:00
Alex Forencich
5e9254d519 Check is_eof_0 in RCSink 2019-10-12 18:58:27 -07:00
Alex Forencich
9b5a5db4d1 Add USPcieFrame intermediate format 2019-10-12 18:01:39 -07:00
Alex Forencich
603a6e18e2 Fix RC channel sideband byte enables 2019-10-11 14:16:44 -07:00
Alex Forencich
b7a505acfd Add segmented DMA RAM simulation model 2019-10-08 15:14:32 -07:00
Alex Forencich
9ab0d50c0a Add PCIe interface tuser width parameters 2019-10-05 13:56:24 -07:00
Alex Forencich
9a1a58f608 Add PCIe interface tuser width parameters 2019-10-04 16:51:07 -07:00
Alex Forencich
4a28adeded merged changes in pcie 2019-10-04 16:29:51 -07:00
Alex Forencich
a92722173a Handle ultrascale plus interface widths 2019-10-04 16:29:11 -07:00
Alex Forencich
e7630ef350 Expose parameter in wrapper 2019-10-02 23:21:49 -07:00
Alex Forencich
1b98af9364 Fix part-select range 2019-10-01 22:00:03 -07:00
Alex Forencich
295b6a507e Use constants instead of magic numbers 2019-10-01 17:30:09 -07:00
Alex Forencich
3817736aa1 Use constants instead of magic numbers 2019-10-01 17:24:18 -07:00
Alex Forencich
1b91200a4a Implement error code 2019-10-01 17:17:42 -07:00
Alex Forencich
b2d9a6a77f Add constants 2019-10-01 17:15:15 -07:00
Alex Forencich
4c4119d44a Use more correct parameters 2019-09-30 22:36:06 -07:00
Alex Forencich
7197e17445 Remove redundant code 2019-09-29 12:57:48 -07:00
Alex Forencich
836246ec4d Add missing asserts 2019-09-29 12:55:53 -07:00
Alex Forencich
a78db05fe2 merged changes in pcie 2019-09-26 23:51:50 -07:00
Alex Forencich
89b7eccb38 Missed some changes 2019-09-26 23:51:18 -07:00
Alex Forencich
e97e4ad423 Parametrize tuser signal widths 2019-09-26 23:30:03 -07:00
Alex Forencich
8678ecee65 Fix bug in AXI operation generation 2019-09-26 23:25:09 -07:00
Alex Forencich
e365ae44da Move AXI transfer size logic to improve timing 2019-09-26 14:39:31 -07:00
Alex Forencich
cddac11486 Bypass check when unnecessary 2019-09-26 14:38:21 -07:00
Alex Forencich
8f73b5605f Fix check 2019-09-26 14:37:41 -07:00
Alex Forencich
2c46513837 Update designs 2019-09-23 18:21:54 -07:00
Alex Forencich
c6e75b40a1 Don't need AXI DMA unaligned support 2019-09-23 18:11:25 -07:00
Alex Forencich
2325966973 Pull out descriptor and completion handling logic 2019-09-23 18:10:35 -07:00
Alex Forencich
6aa48f9127 Add completion op mux module 2019-09-23 14:47:09 -07:00
Alex Forencich
9219957013 Add descriptor op mux module 2019-09-23 14:47:00 -07:00
Alex Forencich
009a80aff2 Add completion write module 2019-09-23 14:44:08 -07:00
Alex Forencich
75a756e915 Add descriptor fetch module 2019-09-23 14:41:35 -07:00
Alex Forencich
835abf9412 Remove pcie_us_axi_master instances and corresponding BAR 2019-09-19 17:31:59 -07:00
Alex Forencich
b5868c8997 Update PTP perout support in VCU108 and VCU118 designs 2019-09-18 19:46:45 -07:00
Alex Forencich
49f9524aeb Update testbenches 2019-09-17 21:46:54 -07:00
Alex Forencich
e3ad96ef07 Add RQ channel passthrough to pcie_us_axi_dma_wr to eliminiate external mux 2019-09-17 16:32:47 -07:00
Alex Forencich
2e27d6ae2f Improve tx_scheduler_rr timing 2019-09-14 23:32:34 -07:00
Alex Forencich
d67a8616fa Enable all queues 2019-09-13 14:19:38 -07:00
Alex Forencich
49103b9df9 Rework interrupt handling 2019-09-13 13:53:36 -07:00
Alex Forencich
bee056e7d3 Fix pipelining bug 2019-09-13 13:48:48 -07:00
Alex Forencich
b59c3c50ed Rename int_index to eq_index 2019-09-12 16:06:22 -07:00
Alex Forencich
9341f93b3f Check PTP feature bits 2019-09-12 10:47:26 -07:00