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155 Commits 1 Branch 0 Tags
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15 Commits

Author SHA1 Message Date
Alex Forencich
5df7efe516 Happy new year 2018-02-26 12:25:20 -08:00
Alex Forencich
1c7362c717 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream frame FIFO 2017-11-20 20:11:44 -08:00
Alex Forencich
aebe0549dd Happy new year 2017-05-18 13:35:11 -07:00
Alex Forencich
0691c9d61b Fix output pipeline issue 2016-09-02 10:43:21 -07:00
Alex Forencich
a961a9756a Add FIFO output pipeline registers to aid block RAM output timing closure 2016-08-04 18:03:00 -07:00
Alex Forencich
6fe4a033e5 Add dedicated pipeline registers for RAM addresses that are not reset 2016-06-27 12:25:18 -07:00
Alex Forencich
385c9cc90a Fix Vivado block RAM inference 2016-06-27 12:10:36 -07:00
Alex Forencich
be4034071b Happy new year 2016-01-05 00:24:20 -08:00
Alex Forencich
0f0ebfb87d Reorganize FIFO modules 2015-11-07 01:15:11 -08:00
Alex Forencich
ca11618e6d Convert to synchronous resets 2015-10-08 11:26:32 -07:00
Alex Forencich
e65173b7ee Add overflow, bad_frame, and good_frame status outputs to frame FIFOs 2015-05-12 17:52:41 -07:00
Alex Forencich
966e47a826 Fix RAM and register widths 2015-04-19 23:06:30 -07:00
Alex Forencich
9b7bad92f2 Reset pointers correctly 2015-04-19 17:51:27 -07:00
Alex Forencich
6e2eda256d Improve frame drop logic in frame FIFOs, add DROP_WHEN_FULL option to disable input tready signal 2015-02-28 19:32:08 -08:00
Alex Forencich
6fa46b6c57 Add AXI frame fifo and testbench 2014-11-08 21:07:47 -08:00