Alex Forencich
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0d9b1d0fb0
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Implement flow control in UltraScale shim
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-26 14:01:00 -07:00 |
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Alex Forencich
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19b1af0388
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Update Xilinx UltraScale shims to support TLP straddling
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-04 00:46:07 -07:00 |
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Alex Forencich
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24dd0af398
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Adjust MSI-X TLP port configuration for single segment, single DWORD operations
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-02 23:41:51 -07:00 |
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Alex Forencich
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27f749d5a5
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Add strobe outputs to shims
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-06-07 14:23:24 -07:00 |
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Alex Forencich
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70dc92c24e
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Rework TLP interface parametrization
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-06-05 13:27:04 -07:00 |
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Alex Forencich
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5208b2844c
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Add MSI-X support to shims
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-06-02 23:35:34 -07:00 |
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Alex Forencich
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90959b8795
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Add default_nettype none and resetall directives
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2021-10-20 17:49:30 -07:00 |
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Alex Forencich
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ac96ae97d3
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Add flow control signals to pcie_us_if
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2021-08-11 19:37:51 -07:00 |
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Alex Forencich
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8e19f6edb8
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Tie off outputs if configuration read functionality is disabled
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2021-08-11 19:17:55 -07:00 |
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Alex Forencich
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836d14bad6
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Add PCIe interface shim for Xilinx UltraScale
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2021-08-04 01:03:31 -07:00 |
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