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Author SHA1 Message Date
Alex Forencich
42cf40f338 merged changes in pcie 2022-05-15 19:27:48 -07:00
Alex Forencich
d685b0b125 Avoid width mismatch warning 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 19:26:10 -07:00
Alex Forencich
234c318ea1 Pipeline arbitration delay in muxes 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 19:25:55 -07:00
Alex Forencich
ae1f4a9a22 Rewrite early ready condition 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 19:25:30 -07:00
Alex Forencich
48e525f62a merged changes in eth 2022-05-15 19:00:00 -07:00
Alex Forencich
80a25731b8 Fix MAC RX PTP timestamp in sideband 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:58:47 -07:00
Alex Forencich
8cdb780ee3 Rewrite resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:57:26 -07:00
Alex Forencich
4b261150d2 Update axis_arb_mux 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:57:02 -07:00
Alex Forencich
609aac39a0 Rewrite early ready condition 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:47:30 -07:00
Alex Forencich
9b5a8cf24a Rewrite resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:39:44 -07:00
Alex Forencich
794eb98789 merged changes in axis 2022-05-15 17:39:11 -07:00
Alex Forencich
ce8dcdafe8 Pipeline arbitration delay in axis_arb_mux 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:36:26 -07:00
Alex Forencich
6d4458e5cc Rewrite early ready condition 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:36:00 -07:00
Alex Forencich
0845058419 Apparently iperf --bidir has issues with getting full BW on RX, so spin up separate TX and RX instances for TX+RX test 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 15:03:02 -07:00
Alex Forencich
cadc811ec6 Set ptp4l tx_timestamp_timeout 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-14 23:54:54 -07:00
Alex Forencich
a897816b2c Add iperf_benchmark script 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-13 16:31:14 -07:00
Alex Forencich
37e9d5655d Add piperf wrapper script 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-13 16:27:59 -07:00
Alex Forencich
ed5b1a9b54 Add PCIe script directory symlink 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-13 16:27:37 -07:00
Alex Forencich
d575230c27 Fix race condition while taking down port 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-13 15:56:26 -07:00
Alex Forencich
268d0c66b8 Rewrite resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-13 12:57:41 -07:00
Alex Forencich
9653caf09b Add 25G mqnic design for Cisco Nexus K3P-Q 2022-05-09 14:02:13 -07:00
Alex Forencich
ba9ef590b7 Use Cisco Nexus part numbers for Cisco Nexus boards 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-09 13:43:47 -07:00
Alex Forencich
835f0d38f0 Update PTP subsystem to use separate clock for improved stability 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-06 17:46:16 -07:00
Alex Forencich
6656a14528 merged changes in eth 2022-05-06 00:22:55 -07:00
Alex Forencich
18d5c325bf Fix CMAC RX PTP timestamps 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-05 23:21:11 -07:00
Alex Forencich
274831c268 Fix PTP clock CDC module timing constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-05 21:41:41 -07:00
Alex Forencich
1eb04bb75b utils: Improve PTP clock period reporting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-05 15:11:26 -07:00
Alex Forencich
7ee0a661bd modules/mqnic: Add kernel version check for ndetdev ioctl change 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-05 11:19:53 -07:00
Alex Forencich
c2fea3a616 Add port register blocks with support for PHY link status reporting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-04 09:03:37 -07:00
Alex Forencich
f67c704b11 Update placement constraints for hierarchy changes 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-02 13:16:20 -07:00
Alex Forencich
cfdd6f5455 Decouple transmit completion handling from PTP timestamping 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-01 17:41:47 -07:00
Alex Forencich
53f3547ef5 Rework hierarchy to move port-specific logic out of mqnic_core and into mqnic_interface and new port-level modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-29 14:32:57 -07:00
Alex Forencich
2d5e82f42a apps: Fix application module symbol search path to include core mqnic module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-25 00:48:56 -07:00
Alex Forencich
56641b3471 modules/mqnic: Export symbols 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-25 00:47:37 -07:00
Alex Forencich
e4de3c2fb5 modules/mqnic: Consistent naming of driver functions and structs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-24 23:01:15 -07:00
Alex Forencich
cc9d445005 Move driver-specific code out of mqnic_hw.h 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-24 22:54:04 -07:00
Alex Forencich
698fd2f104 Consistent naming of library functions and structs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-24 22:51:37 -07:00
Alex Forencich
d5c2566dff Add statistics collection for AXI DMA IF 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-23 13:12:50 -07:00
Alex Forencich
2bd8350276 Add RX queue mapping module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-23 00:12:22 -07:00
Alex Forencich
1b3caa1f0f Fix reg block enumeration to properly handle NULL register blocks 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-22 23:27:15 -07:00
Alex Forencich
f4d2662dff Fix find_reg_block handling of NULL register blocks 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-22 23:25:15 -07:00
Alex Forencich
28bbae908b fpga/common: Store receive queue index in packet object in driver model 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-22 19:04:26 -07:00
Alex Forencich
5ae58e751f modules/mqnic: Use eth_hw_addr_set when available 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-22 18:46:40 -07:00
Alex Forencich
ba70ae2521 fpga/mqnic/fb2CG: Add integrations for template and DMA benchmark applications on fb2CG@KU15P 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-21 14:20:40 -07:00
Alex Forencich
d45857fb98 fpga/app/dma_bench: Add DMA benchmark application 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-21 14:19:43 -07:00
Alex Forencich
6044b75fa3 fpga/app/template: Add extension kernel module for template application 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-21 13:43:36 -07:00
Alex Forencich
e2cf0947ae fpga/app/template: Add utility for template application 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-21 13:42:56 -07:00
Alex Forencich
65a986cc89 modules/mqnic: Add support for extension kernel modules using the auxiliary bus 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-21 13:18:00 -07:00
Alex Forencich
7f8bbe30de Add application ID 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-21 13:15:45 -07:00
Alex Forencich
dbe0dc70ee modules/mqnic: Remove obsolete PHC entries 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-20 21:29:56 -07:00