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mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00

43 Commits

Author SHA1 Message Date
Alex Forencich
5fe35a79d2 Add tdest support to axis_ep 2016-07-25 11:28:35 -07:00
Alex Forencich
be4034071b Happy new year 2016-01-05 00:24:20 -08:00
Alex Forencich
364b537312 Synchronize status signals for both clock domains in async frame FIFO 2015-10-09 15:14:54 -07:00
Alex Forencich
30a35c3d73 Convert async fifo to common reset 2015-10-08 12:52:51 -07:00
Alex Forencich
120f86f4cf Add SRL FIFO reset tests 2015-07-13 23:15:39 -07:00
Alex Forencich
516c50d786 Add FIFO reset tests 2015-07-09 11:13:25 -07:00
Alex Forencich
87fe1a561f Add AXI stream tap modules 2015-06-22 14:56:56 -07:00
Alex Forencich
c15761068a Add AXI stream frame length adjust modules 2015-06-05 17:04:10 -07:00
Alex Forencich
e72b93033d Add parameters to axis_stat_counter testbench 2015-05-12 17:54:37 -07:00
Alex Forencich
e65173b7ee Add overflow, bad_frame, and good_frame status outputs to frame FIFOs 2015-05-12 17:52:41 -07:00
Alex Forencich
14f2d5e9f7 Add tkeep asserts to AXI stream EP 2015-05-03 00:23:58 -07:00
Alex Forencich
7b991bfe0e Update AXI stream endpoint to support multiple tdata signals 2015-03-21 03:35:42 -07:00
Alex Forencich
02a7f4d5ed Update testbenches to python 3 2015-03-21 03:32:19 -07:00
Alex Forencich
54bfdaa8c0 Cast WL to int 2015-03-21 03:19:43 -07:00
Alex Forencich
3138795899 Fix rate limiter testbenches 2015-03-21 02:55:30 -07:00
Alex Forencich
6e2eda256d Improve frame drop logic in frame FIFOs, add DROP_WHEN_FULL option to disable input tready signal 2015-02-28 19:32:08 -08:00
Alex Forencich
3c7e3b0424 Add SRL register module and testbench 2014-12-03 18:51:46 -08:00
Alex Forencich
10fd51f192 Add SRL FIFO module and testbench 2014-12-03 18:49:33 -08:00
Alex Forencich
b07c2d63b0 Parametrize tag and counter widths 2014-11-19 23:06:43 -08:00
Alex Forencich
0c3af7d5bb Reverse priority in arbitrated mux 2014-11-16 02:00:27 -08:00
Alex Forencich
b123525597 Add enable signal 2014-11-16 01:38:20 -08:00
Alex Forencich
5f0d23a3ad Add AXI arbitrated mux module and testbench 2014-11-13 02:01:45 -08:00
Alex Forencich
a8970e6e75 Change block parameter 2014-11-13 02:01:07 -08:00
Alex Forencich
a1633f27d8 Add arbiter module 2014-11-13 01:22:59 -08:00
Alex Forencich
3399f284b2 Add priority encoder 2014-11-12 23:59:02 -08:00
Alex Forencich
5c49ed6191 Add AXI stream demux and testbench 2014-11-12 19:21:28 -08:00
Alex Forencich
5af6dc3501 Add AXI stream mux and testbench 2014-11-12 15:49:07 -08:00
Alex Forencich
a28a534bff Add AXI stream crosspoint module and testbench 2014-11-12 01:54:31 -08:00
Alex Forencich
10e0d7d1bb Add AXI async frame fifo and testbench 2014-11-08 21:29:39 -08:00
Alex Forencich
6fa46b6c57 Add AXI frame fifo and testbench 2014-11-08 21:07:47 -08:00
Alex Forencich
918ef8f76c Add AXI async FIFO and testbench 2014-11-08 00:23:23 -08:00
Alex Forencich
ac2f7e546d Adjust syntax for old Python 2 2014-11-05 16:40:27 -08:00
Alex Forencich
e8c43653e3 Adjust syntax for old Python 2 2014-11-05 16:33:33 -08:00
Alex Forencich
7c3adb6c2b Add AXI stream frame joiner, generator, and testbench 2014-10-22 10:47:03 -07:00
Alex Forencich
3b1655f81f Update rate limit test bench to check more settings and verify rate 2014-10-21 23:25:28 -07:00
Alex Forencich
67bb09ba42 Add busy output to statistics collection module 2014-10-21 16:09:55 -07:00
Alex Forencich
f22381baa2 Initial commit of basic statistics collection module 2014-10-21 13:20:37 -07:00
Alex Forencich
377ef5accb Initial commit of AXI stream rate limiter 2014-10-20 15:09:07 -07:00
Alex Forencich
e0c2f44dc2 Initial commit of AXI stream width adapter 2014-10-20 15:04:36 -07:00
Alex Forencich
54bc201f52 Always make a copy of the data array 2014-09-19 17:32:27 -07:00
Alex Forencich
e1955a29da Add LocalLink to AXI stream bridge 2014-09-13 21:23:11 -07:00
Alex Forencich
74fa967071 Add AXI stream register 2014-09-13 21:22:06 -07:00
Alex Forencich
35f39a6f4b Add AXI stream FIFO 2014-09-13 21:21:39 -07:00