Alex Forencich
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75c2cc0acc
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Use quad wrappers in HTG9200 example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-08-25 01:24:26 -07:00 |
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Alex Forencich
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aaeeb05ac0
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Fix PHY configuration connections
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-08-25 00:09:38 -07:00 |
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Alex Forencich
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fa05d4ff3c
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Add TX and RX enable inputs to MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-08-24 01:24:33 -07:00 |
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Alex Forencich
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20c542051d
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Use cfg prefix for configuration signals
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-08-22 17:14:52 -07:00 |
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Alex Forencich
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bdc974a60c
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Reorganize HTG-9200 PLL config
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-21 16:34:11 -07:00 |
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Alex Forencich
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4a65e3594c
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Connect all PLL control lines on HTG-9200 board
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-20 01:17:49 -07:00 |
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Alex Forencich
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d3fb11b2c3
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Use unified 10G/25G design for HTG9200
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-13 21:35:42 -07:00 |
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