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Author SHA1 Message Date
Alex Forencich
6020d09214 Reorganize FIFO write logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 18:55:02 -07:00
Alex Forencich
c3cd676c5d Test DROP_WHEN_FULL parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:59:57 -07:00
Alex Forencich
c4f298de6f Add overflow test, previous test is actually an oversize frame test 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:59:30 -07:00
Alex Forencich
330d6f41fc Send more data in stress tests 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:59:14 -07:00
Alex Forencich
3a665f0ded Compute DEPTH based on FIFO data width 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:58:35 -07:00
Alex Forencich
7febd080c9 Use FIFO depth in overflow test 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:58:22 -07:00
Alex Forencich
ac2c0fdac8 Read configuration directly from DUT 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:57:30 -07:00
Alex Forencich
62c2148c8f Add pause functionality to FIFO modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:57:16 -07:00
Alex Forencich
e308c9559a Rewrite width converter to reduce resource consumption 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:56:54 -07:00
Alex Forencich
31bac4e21f Reorganize FIFO adapter wrappers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:56:33 -07:00
Alex Forencich
1628a1a043 Reorganize pipeline FIFO to facilitate placement constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-27 01:43:36 -07:00
Alex Forencich
10da93fec4 Add depth status outputs to FIFOs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-26 20:02:43 -07:00
Alex Forencich
2be72bb758 Refactor pointer handling in FIFOs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-26 18:47:43 -07:00
Alex Forencich
9cb38fa2a0 Remove extraneous parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-26 16:48:28 -07:00
Alex Forencich
9bc052de8b Another update to async FIFO timing constraints to deal with OOC clock constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-26 14:53:01 -07:00
Alex Forencich
960a2eab61 Remove recursively-expanded macros for module parameters in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 15:56:40 -08:00
Alex Forencich
5f1ad94041 Update ubuntu version in CI 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-13 13:03:06 -08:00
Alex Forencich
b81e323a6d Rework parameter handling in testbench makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-29 20:53:11 -08:00
Alex Forencich
e6d8ed7992 Update CI configuration 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-25 19:10:09 -08:00
Alex Forencich
786e971f40 Remove separate memory read register (it causes ISE to crash, and is not necessary for URAM inference) 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-29 23:54:17 -08:00
Alex Forencich
46bd4302de Update async FIFO timing constraints to handle clocks from OOC IP that are not constrained during synthesis 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-08 18:49:21 -08:00
Alex Forencich
ed6130575d Update async FIFO timing constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 23:27:39 -07:00
Alex Forencich
9c3409f9d7 Add option for output FIFO to improve pipelining and RAM inference for large FIFOs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 19:02:53 -07:00
Alex Forencich
d4cf84ccf0 Consolidated RAM pipeline output wires 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 16:36:11 -07:00
Alex Forencich
6f761bc4a5 Use separate RAM output register for better pipeline register inference 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 14:46:24 -07:00
Alex Forencich
a0f46801a1 Replace OUTPUT_PIPELINE with RAM_PIPELINE 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 14:40:58 -07:00
Alex Forencich
fa4e8e70cb Add intermediate signal for end of FIFO RAM pipeline 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 14:03:51 -07:00
Alex Forencich
b9e0af3634 Revert change to early ready conditions for improved throughput 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-18 12:07:11 -07:00
Alex Forencich
fc5964ab90 Update package versions 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-07 20:00:01 -07:00
Alex Forencich
ce8dcdafe8 Pipeline arbitration delay in axis_arb_mux 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:36:26 -07:00
Alex Forencich
6d4458e5cc Rewrite early ready condition 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:36:00 -07:00
Alex Forencich
268d0c66b8 Rewrite resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-13 12:57:41 -07:00
Alex Forencich
073d50d9dc Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8 2022-03-30 16:02:17 -07:00
Alex Forencich
96716b0556 Lock package versions 2021-12-27 16:54:24 -08:00
Alex Forencich
fef6b167bc Specify min tox and venv versions 2021-12-27 16:53:40 -08:00
Alex Forencich
61fbb2d76f Use available python 3 2021-12-27 16:51:58 -08:00
Alex Forencich
4df34f1344 Use start_soon instead of fork 2021-12-10 18:16:38 -08:00
Alex Forencich
2a89fb9332 Testbench parameter cleanup 2021-11-29 01:01:45 -08:00
Alex Forencich
e4b4762474 Handle some zero-valued signal width settings 2021-11-29 00:33:38 -08:00
Alex Forencich
907081d255 Add support to demux for routing by tdest 2021-11-28 23:09:10 -08:00
Alex Forencich
ccbca0c502 Add UPDATE_TID parameter to set MSBs of tid based on source port 2021-11-28 16:25:35 -08:00
Alex Forencich
24863398c5 Decouple tid/tdest signal widths for routing components 2021-11-25 01:18:51 -08:00
Alex Forencich
150d5ad04e Handle out-of-range select as drop 2021-11-24 14:58:16 -08:00
Alex Forencich
f40e68350c Remove deprecated assigments 2021-11-15 14:39:47 -08:00
Alex Forencich
96a26e7a54 Add attributes to RAMs for proper synthesis in Quartus 2021-11-02 20:22:47 -07:00
Alex Forencich
2972a1fa81 Add default_nettype none and resetall directives 2021-10-20 15:33:38 -07:00
Alex Forencich
2cd70281ea Properly zero synchronized pointer on one-sided reset 2021-10-17 01:23:02 -07:00
Alex Forencich
10e24cc5b1 Fix timing constraints 2021-10-13 18:07:45 -07:00
Alex Forencich
4f1eabab17 Split async FIFO resets 2021-10-13 14:05:13 -07:00
Alex Forencich
e0da1819c4 More tests for pipeline FIFO 2021-09-28 01:18:17 -07:00