FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity
2,687 Commits 1 Branch 0 Tags
Commit Graph

361 Commits

Author SHA1 Message Date
Alex Forencich
57905a5ef9 fpga/mqnic/ZCU106/fpga_zynqmp: Rewrite zynq PS TCL script, rework PS clock settings, switch to 300 MHz PL clock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-11 12:25:51 -07:00
Alex Forencich
72d8583235 fpga/mqnic/ZCU106/fpga_zynqmp: Remove unused I2C interface 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-11 10:54:58 -07:00
Alex Forencich
4b4922c858 fpga/mqnic: Add 10G mqnic design for DNPCIe_40G_KU_LL_2QSFP 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-09 23:03:31 -07:00
Alex Forencich
c5d5fe8a64 fpga/mqnic: Remove unused wires 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-09 23:02:44 -07:00
Alex Forencich
1bb7053a68 ZCU106/fpga_zynqmp: Add integration test 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-07 21:42:01 -07:00
Alex Forencich
5f7c051b5b ZCU106/fpga_zynqmp: Sync module parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-07 21:41:06 -07:00
Alex Forencich
2eb4e5c4bd ZCU106/fpga_zynqmp/ps/petalinux/: Enable PTP in kernel and add linuxptp package 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-07 19:23:36 -07:00
Joachim Foerster
eb17563097 ZCU106/fpga_zynqmp/ps/petalinux/: Add shortcut Makefile target "build-boot" to build PetaLinux including boot files in one step 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-04-07 18:41:05 +02:00
Joachim Foerster
2252308dc2 ZCU106/fpga_zynqmp/: README: Provide more information on how to build and test 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-04-07 18:41:05 +02:00
Joachim Foerster
1191908e68 ZCU106/fpga_zynqmp/ps/petalinux/: rootfs: Enable and include layer meta-corundum and its recipes 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-04-07 18:41:05 +02:00
Joachim Foerster
442a24c5a7 ZCU106/fpga_zynqmp/ps/petalinux/: rootfs: Include various kernel module and network device tools 
- kmod (for modinfo)
- ethtool
- net-tools (for arp)
- iputils-ping (for ping; Busybox' ping does not support flood ping option)
- iproute2 (for ip; Busybox' ip is very limited)
- tcpdump
- iperf2

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
 2022-04-07 18:41:05 +02:00
Joachim Foerster
5700aba9a0 ZCU106/fpga_zynqmp/ps/petalinux/: dts: Add custom device tree node for mqnic device 
Currently consists of 4 parts:
- Removing stub nodes generated by Xilinx device tree generator.
- Adding a custom, manually edited node (needs manual adjustment in case PS
  settings are changed!)
  NOTE: In the future this node might be reduced or removed all together after
  having added a plugin for Xilinx' device tree generator
  (https://github.com/Xilinx/device-tree-xlnx.git), which properly automatically
  generates such a node.
- Adding eeprom nodes for the SFP module I2C buses.
- Disabling the node for the USER MGT SI570 (U56) chip to make Linux NOT touch
  this chip on startup. See lengthy comment.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
 2022-04-07 18:41:05 +02:00
Joachim Foerster
2dbea0f913 ZCU106/fpga_zynqmp/ps/petalinux/: Add basic PetaLinux v2021.1 project 
- modify .gitignore compared to generated version by petalinux-create;
  to avoid committing unnecessary files (binaries, toolchain leftovers, ...)
- set machine name to "zcu106-reva"
- disable "copy to tftpboot directory"
- enable FSBL detailed debug output

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-04-07 17:14:57 +02:00
Joachim Foerster
80d5bda23f ZCU106/fpga_zynqmp: Fix maximum burst length for AXI Master 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-03-31 17:24:16 +02:00
Joachim Foerster
62879ff3ea ZCU106/fpga_zynqmp: Support parameter EVENT_QUEUE_INDEX_WIDTH, reduce Events queues to number of CPU cores 
- Keep parameter defaults in Verilog file at global of 32, though
- Select 4 Event queues via config.tcl, only

Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-03-31 17:24:16 +02:00
Andreas Braun
dc77c9e92a ZCU106/fpga_zynqmp: Reduce number of IRQs to number of CPU cores 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
 2022-03-31 17:22:27 +02:00
Andreas Braun
dce11522fa ZCU106/fpga_zynqmp: Reduce number of RX/TX queues to 32 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-03-31 17:22:27 +02:00
Andreas Braun
35517037e6 ZCU106/: Add design based on ZynqMP PS as host system, Vivado v2021.1 
Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
Signed-off-by: Joachim Förster <joachim.foerster@missinglinkelectronics.com>
 2022-03-31 17:22:27 +02:00
Alex Forencich
f082196b4a Expose EVENT_QUEUE_INDEX_WIDTH parameter at top-level 2022-03-29 23:15:06 -07:00
Alex Forencich
cbd9d0dfc6 Expose port and scheduler block counts in IF control block; update driver model, driver, and userspace tools to handle scheduler blocks separately from ports 2022-03-28 17:23:27 -07:00
Alex Forencich
09128df360 Add SCHED_PER_IF parameter to split scheduler count from port count 2022-03-28 15:20:33 -07:00
Alex Forencich
dfae34ed25 Pass through PTP pipelining settings 2022-03-28 00:50:29 -07:00
Alex Forencich
e95c132045 Route PCIe user reset through BUFG 2022-03-25 01:26:29 -07:00
Alex Forencich
6f197c7cb4 Add PHY instances to Ethernet pblocks 2022-03-24 21:30:55 -07:00
Alex Forencich
8aa2185bfb Fix MCS file addresses for main bitstream 2022-03-20 22:52:14 -07:00
Alex Forencich
b83270c953 Fix rev file numbering for fallback bitstream generation 2022-03-20 22:50:37 -07:00
Alex Forencich
056f78716a Add pipeline registers 2022-03-17 15:39:44 -07:00
Alex Forencich
0e15a7a16b Avoid critical warning from placement constraints when configured with a single interface 2022-03-17 15:39:13 -07:00
Alex Forencich
869e7e70d4 Add Ethernet interface placement constraints for AU250 2022-03-17 00:51:14 -07:00
Alex Forencich
059d9b5e37 Add Ethernet interface placement constraints for AU200 2022-03-17 00:51:05 -07:00
Alex Forencich
28558449f6 Add Ethernet interface placement constraints for VCU1525 2022-03-17 00:48:52 -07:00
Alex Forencich
0928f56a45 Add Ethernet interface placement constraints for VCU118 2022-03-17 00:48:44 -07:00
Alex Forencich
a61ac12962 Add Ethernet interface placement constraints for ADM-PCIE-9V3 2022-03-16 21:08:01 -07:00
Alex Forencich
e317439843 Add Ethernet interface placement constraints for fb2CG@KU15P 2022-03-16 21:07:53 -07:00
Alex Forencich
1291d7b1b7 Add pipeline registers to TDMA BER modules 2022-03-15 17:40:27 -07:00
Alex Forencich
25421b8994 Update placement constraints 2022-03-15 15:28:43 -07:00
Alex Forencich
39691759aa Unified 10G/25G design for VCU118 2022-03-14 21:40:29 -07:00
Alex Forencich
202f407686 Unified 10G/25G design for VCU1525 2022-03-14 21:39:55 -07:00
Alex Forencich
b10ff8b4a7 Unified 10G/25G design for AU250 2022-03-14 21:39:13 -07:00
Alex Forencich
74be2d9b57 Unified 10G/25G design for AU200 2022-03-14 21:38:31 -07:00
Alex Forencich
2024ac60ec Unified 10G/25G design for AU280 2022-03-14 21:37:40 -07:00
Alex Forencich
67bd69a8d7 Unified 10G/25G design for AU50 2022-03-14 21:36:30 -07:00
Alex Forencich
e9d52516fb Unified 10G/25G design for ExaNIC X25 2022-03-14 19:12:58 -07:00
Alex Forencich
1fadd2f361 Unified 10G/25G design for ADM-PCIE-9V3 2022-03-14 18:50:40 -07:00
Alex Forencich
e5c6f7cf01 Unified 10G/25G design for fb2CG@KU15P 2022-03-14 17:44:31 -07:00
Alex Forencich
8168469ec8 Update config.tcl 2022-03-14 14:45:38 -07:00
Alex Forencich
8e2e6c6026 Fix testbench 2022-03-04 00:01:33 -08:00
Alex Forencich
d9e79c9923 Rename cores to match transceiver type 2022-03-03 22:41:34 -08:00
Alex Forencich
29f97dc663 Update ZCU106 to use new wrapper 2022-03-03 22:26:06 -08:00
Alex Forencich
a373753d6e Update VCU108 to use new wrapper 2022-03-03 22:23:43 -08:00