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2,687 Commits 1 Branch 0 Tags
Commit Graph

361 Commits

Author SHA1 Message Date
Alex Forencich
3ef15abcef Update VCU118 to use new wrapper 2022-03-03 22:14:18 -08:00
Alex Forencich
59eac3d2e5 Update ExaNIC X10 to use new wrapper 2022-03-03 20:38:55 -08:00
Alex Forencich
16111eb7a8 Update AU50 to use new wrapper 2022-03-03 20:15:06 -08:00
Alex Forencich
8fff75577a Update AU280 to use new wrapper 2022-03-03 19:53:49 -08:00
Alex Forencich
3472efd219 Update AU250 to use new wrapper 2022-03-03 17:49:08 -08:00
Alex Forencich
f8950897bc Update AU200 to use new wrapper 2022-03-03 17:34:42 -08:00
Alex Forencich
180ff33c7e Update VCU1525 to use new wrapper 2022-03-03 17:03:24 -08:00
Alex Forencich
37a4c41636 Update ADM-PCIE-9V3 to use new wrapper 2022-03-03 15:40:36 -08:00
Alex Forencich
7bbc777c98 Update ExaNIC X25 to use new wrapper 2022-03-03 15:32:17 -08:00
Alex Forencich
2cc3dbd5cc Update DRP info 2022-03-02 23:12:02 -08:00
Alex Forencich
a54b673d54 Explicitly set equalizer mode 2022-03-02 23:11:49 -08:00
Alex Forencich
348aae9687 Update fb2CG@KU15P designs to use new wrapper 2022-03-02 17:38:47 -08:00
Alex Forencich
2909d205de Remove unused files 2022-02-16 17:40:28 -08:00
Alex Forencich
3997e0d95b Parametriztion updates, add RAM_ADDR_WIDTH as a top-level parameter 2022-02-15 18:01:43 -08:00
Alex Forencich
c98258bf05 Fix parametrization 2022-02-13 23:19:09 -08:00
Alex Forencich
627ac359d5 Add layer 2 ingress/egress modules 2022-02-13 23:09:41 -08:00
Alex Forencich
b7bc240aa6 Add JTAG and GPIO passthroughs to application section 2022-01-27 23:06:05 -08:00
Alex Forencich
aab30c8cd0 Add transceiver quad wrappers 2022-01-16 18:28:22 -08:00
Alex Forencich
335a5e890b Initial implementation of shared interface datapath 2021-12-31 14:33:31 -08:00
Alex Forencich
ce21774f06 Register space reorganization 2021-12-29 22:31:46 -08:00
Alex Forencich
8548e8570f Update vivado.mk 2021-12-20 22:03:06 -08:00
Alex Forencich
7a43618e3c Use start_soon instead of fork 2021-12-10 20:43:21 -08:00
Alex Forencich
bc8a8cdc58 Update 100G designs to use correct clock for PTP RX timestamps 2021-11-19 01:54:58 -08:00
Alex Forencich
886111c9e6 Update 10G designs for PTP separate RX clock 2021-11-19 01:52:23 -08:00
Alex Forencich
af3b6312a9 Add PTP_USE_SAMPLE_CLOCK parameter to testbenches 2021-11-18 21:12:06 -08:00
Alex Forencich
5bf9de656c Update testbenches 2021-11-17 18:08:40 -08:00
Alex Forencich
76e18d2af8 Add 10G mqnic design for Stratix 10 MX dev kit 2021-11-07 13:59:05 -08:00
Alex Forencich
38c85a6bcd Set subsystem ID based on board, remove unnecessary configuration settings 2021-11-02 15:32:55 -07:00
Alex Forencich
dbd15cb60e Rework GT instances in VCU118 10G design 2021-10-21 22:16:05 -07:00
Alex Forencich
6e7109a3a0 Rework GT instances in VCU1525 10G design 2021-10-21 21:50:06 -07:00
Alex Forencich
b8eb3806a4 Rework GT instances in Alveo U280 10G design 2021-10-21 21:49:27 -07:00
Alex Forencich
bc7635e5dc Rework GT instances in Alveo U250 10G design 2021-10-21 21:48:49 -07:00
Alex Forencich
6a7a91856f Rework GT instances in Alveo U200 10G design 2021-10-21 19:58:22 -07:00
Alex Forencich
01871e46cb Rework GT instances in Alveo U50 10G design 2021-10-21 19:57:17 -07:00
Alex Forencich
6876ad4593 Rework GT instances in ZCU106 design 2021-10-21 19:00:47 -07:00
Alex Forencich
8f15664092 Rework GT instances in VCU118 design 2021-10-21 18:50:55 -07:00
Alex Forencich
cfe41e9680 Rework GT instances in ADM-PCIE-9V3 10G and 25G designs 2021-10-21 17:49:08 -07:00
Alex Forencich
2f5c15f513 Rework GT instances in fb2CG@KU15P 10G and 25G designs 2021-10-21 16:31:36 -07:00
Alex Forencich
d528949aa9 Rework GT instances in ExaNIC X10 design 2021-10-21 16:30:13 -07:00
Alex Forencich
5eca6389cf Rework GT instances in ExaNIC X25 10G and 25G designs 2021-10-21 16:29:48 -07:00
Alex Forencich
7ac4797336 Add default_nettype none and resetall directives 2021-10-20 21:53:39 -07:00
Alex Forencich
607257d7bb Fix connections 2021-10-20 20:43:11 -07:00
Alex Forencich
982edfeda7 Update file lists 2021-10-20 19:37:37 -07:00
Alex Forencich
780406197d Add 25G mqnic design for ExaNIC X25 2021-09-26 18:11:00 -07:00
Alex Forencich
92bb1bda57 Remove unused files 2021-09-26 18:00:36 -07:00
Alex Forencich
45b7e3566c Update readme 2021-09-26 01:16:34 -07:00
Alex Forencich
c8e6484af7 Use correct width for full throughput at 25G 2021-09-26 01:04:40 -07:00
Alex Forencich
39fbc194fd Update makefiles 2021-09-20 18:22:47 -07:00
Alex Forencich
cc6348653d Add TDMA variants 2021-09-13 17:19:50 -07:00
Alex Forencich
b1596751cf Update NetFPGA SUME design 2021-09-13 01:30:36 -07:00