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394 Commits

Author SHA1 Message Date
Alex Forencich
61caf147f7 Use CMAC wrapper in 100G mqnic design for XUP-P3R 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 18:26:10 -08:00
Alex Forencich
596db2d756 Use CMAC wrapper in 100G mqnic design for VCU118 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 18:24:43 -08:00
Alex Forencich
db621ffa7d Use CMAC wrapper in 100G mqnic design for 250-SoC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 18:01:43 -08:00
Alex Forencich
cdda035427 Use CMAC wrapper in 100G mqnic design for VCU1525 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 17:35:09 -08:00
Alex Forencich
e51e5a84af Use CMAC wrapper in 100G mqnic design for Alveo U50 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 17:07:12 -08:00
Alex Forencich
39c5744e99 Use CMAC wrapper in 100G mqnic design for Alveo U280 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 16:30:55 -08:00
Alex Forencich
3d993e4479 Use CMAC wrapper in 100G mqnic design for Alveo U250 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 16:00:45 -08:00
Alex Forencich
f67bd98719 Use CMAC wrapper in 100G mqnic design for Alveo U200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 12:38:14 -08:00
Alex Forencich
49be896333 Use CMAC wrapper in 100G mqnic design for ADM-PCIE-9V3 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 11:49:34 -08:00
Alex Forencich
f70f4d9b90 Use CMAC wrapper in 100G mqnic design for fb2CG@KU15P 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 11:42:07 -08:00
Alex Forencich
8c733dff9e fpga/mqnic/fb2CG: Update placement constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-17 13:01:16 -07:00
Alex Forencich
e3f2d8990d fpga/mqnic: Use all ports for TDMA designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-15 23:30:54 -07:00
Alex Forencich
d3942da875 fpga: Add clock info register block 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-15 19:45:02 -07:00
Alex Forencich
6fa30bc94c fpga/mqnic: Fix critical warnings when MIGs are not present 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-15 13:47:41 -07:00
Alex Forencich
d0cc106783 fpga: Remove redundant RX_RSS_ENABLE parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-13 17:10:25 -07:00
Alex Forencich
01df80df86 fpga/mqnic: Disable MIGs by default 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 23:57:27 -07:00
Alex Forencich
5e52a52f5e fpga/mqnic: Add MIGs and HBM controllers for most boards 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 19:00:49 -07:00
Alex Forencich
eb990643f2 fpga/mqnic: various minor cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 17:12:07 -07:00
Alex Forencich
5f1e74b0e1 Add PROJECT variable, remove multiple stem matches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-11 13:33:09 -07:00
Alex Forencich
7017e7d49b Explicitly set top module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-11 12:29:01 -07:00
Alex Forencich
ceb6a9ca06 Update clean target 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-11 12:26:39 -07:00
Alex Forencich
9c98f12392 Write debug probes file alongside bit file 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-10 23:37:54 -07:00
Alex Forencich
9628401780 Normalize output file location 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-10 21:47:53 -07:00
Alex Forencich
caf2a0993b fpga: Output hierarchical utilization reports 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-06 21:17:25 -07:00
Alex Forencich
d7904b8007 fpga: Add support for IRQ rate limiting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 15:24:40 -07:00
Alex Forencich
1486da601f fpga: Add clock period parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 12:03:35 -07:00
Alex Forencich
647a168299 Enable more peripherals in Zynq designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-16 18:49:02 -07:00
Alex Forencich
1b9f5d1032 fpga/mqnic/ZCU102: Add 10G mqnic design for ZCU102 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-16 01:44:52 -07:00
Alex Forencich
171c2a9a69 fpga/mqnic/ZCU106/fpga_zynqmp: Remove SI570 workaround 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-15 23:54:02 -07:00
Alex Forencich
d0ce01de7f fpga/mqnic/S10DX_DK: fix typo 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-05 16:28:15 -07:00
Alex Forencich
6c6648f114 fpga/mqnic: Add RAM inference directive to Intel designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-05 16:27:29 -07:00
Alex Forencich
81648cf85b fpga/mqnic: Clean up PCIe DMA IF flow control connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 23:04:05 -07:00
Alex Forencich
3f57c2143b fpga/mqnic: PCIe interface updates 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 12:28:49 -07:00
Alex Forencich
607ce498cf fpga/mqnic: Update PCIe DMA settings on Intel designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 00:42:19 -07:00
Alex Forencich
4bcac62c2a fpga/mqnic: Disable PTP on 100G E-tile designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 00:41:53 -07:00
Alex Forencich
0afe9be906 fpga/mqnic/VCU108: Update VCU108 design to support 25G 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-26 23:26:11 -07:00
Alex Forencich
6a29073aa6 fpga/mqnic/S10MX_DK: Update S10MX dev kit design to support 25G 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-25 21:25:21 -07:00
Alex Forencich
2a10dc1582 fpga/mqnic/S10MX_DK: Annotate serdes pins in QSF 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-23 19:43:21 -07:00
Alex Forencich
2c602b6368 Add 25g mqnic design for Stratix 10 DX dev kit 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-23 19:42:58 -07:00
Alex Forencich
ec17500a66 Add 100G mqnic design for DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-21 18:49:35 -07:00
Alex Forencich
ae5a029720 Update PCIe model configuration 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-21 18:49:17 -07:00
Alex Forencich
03a49d7bc6 Add 25G mqnic design for DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-19 23:43:22 -07:00
Alex Forencich
218f2e2bb3 25G designs use double width sync datapath by default 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 23:31:36 -07:00
Alex Forencich
c76e152804 Rename cmac_ts_insert to mac_ts_insert 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:27:27 -07:00
Alex Forencich
e47175e5f2 Add 100G mqnic design for BittWare 250-SoC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:26:22 -07:00
Alex Forencich
7235484825 Add 25G mqnic design for BittWare 250-SoC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:26:12 -07:00
Alex Forencich
ef5b2449dc Add stretched PTP PPS output 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:25:58 -07:00
Alex Forencich
676f3edd2d Add TX PTP clock to port map module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:25:39 -07:00
Alex Forencich
b1240bdcae Remove extraneous wires 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:25:10 -07:00
Alex Forencich
2baae23f94 Minor cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:24:55 -07:00