501 Commits

Author	SHA1	Message	Date
Alex Forencich	627ac359d5	Add layer 2 ingress/egress modules	2022-02-13 23:09:41 -08:00
Alex Forencich	01f0631ddb	Update parameters	2022-02-11 22:04:04 -08:00
Alex Forencich	69ec8a9b52	merged changes in pcie	2022-02-03 00:58:24 -08:00
Alex Forencich	defdbb14df	merged changes in axi	2022-02-03 00:58:18 -08:00
Alex Forencich	440e6a06a2	merged changes in eth	2022-02-03 00:57:55 -08:00
Alex Forencich	e86d47f667	Improve parameter handling in start_xmit	2022-01-27 23:42:32 -08:00
Alex Forencich	155aa5caae	Block in start_xmit when ring is full	2022-01-27 23:34:38 -08:00
Alex Forencich	f98d831014	Ensure that info ring location is empty when sending packets	2022-01-27 23:21:32 -08:00
Alex Forencich	b7bc240aa6	Add JTAG and GPIO passthroughs to application section	2022-01-27 23:06:05 -08:00
Alex Forencich	36bd1f78b0	Add missing parameter connection in rx_fifo	2022-01-26 09:44:35 -08:00
Alex Forencich	2132a8d98f	Fix index handling in driver model	2022-01-26 09:30:41 -08:00
Alex Forencich	aab30c8cd0	Add transceiver quad wrappers	2022-01-16 18:28:22 -08:00
Alex Forencich	137a6778da	Combine interface control blocks	2022-01-15 21:53:13 -08:00
Alex Forencich	ddd7e639da	Add tdest register to scheduler blocks	2021-12-31 17:02:59 -08:00
Alex Forencich	335a5e890b	Initial implementation of shared interface datapath	2021-12-31 14:33:31 -08:00
Alex Forencich	ce21774f06	Register space reorganization	2021-12-29 22:31:46 -08:00
Alex Forencich	6163efa0b8	Add output pipeline stage to descriptor FIFOs	2021-12-29 14:30:05 -08:00
Alex Forencich	8548e8570f	Update vivado.mk	2021-12-20 22:03:06 -08:00
Ulrich Langenbach	0560f98e79	support more than 4k queues (workaround quartus loop iteration limit)	2021-12-16 12:09:39 -08:00
Alex Forencich	7a43618e3c	Use start_soon instead of fork	2021-12-10 20:43:21 -08:00
Alex Forencich	ae2f64f6ba	merged changes in eth	2021-12-10 18:50:07 -08:00
Alex Forencich	f8a1339581	merged changes in axi	2021-12-10 18:50:04 -08:00
Alex Forencich	b8e55944b1	merged changes in pcie	2021-12-10 18:42:24 -08:00
Alex Forencich	bbb9f42516	merged changes in pcie	2021-12-02 17:00:11 -08:00
Alex Forencich	7e3d8606fc	Rework window creation	2021-12-02 16:46:56 -08:00
Alex Forencich	540e7eb1de	Fix offset	2021-12-02 16:46:35 -08:00
Alex Forencich	089c405c4f	Fix clock connections	2021-11-30 16:39:27 -08:00
Alex Forencich	8674bd1e69	Update app testbench	2021-11-30 15:36:38 -08:00
Alex Forencich	720a06ca8b	Update mux instances	2021-11-30 15:36:24 -08:00
Alex Forencich	bbc94af35e	merged changes in eth	2021-11-30 14:41:16 -08:00
Alex Forencich	ebd80e7267	Test multiple ports	2021-11-30 14:12:34 -08:00
Alex Forencich	9d817af8d1	Test all interfaces	2021-11-30 00:57:41 -08:00
Alex Forencich	639117e53f	Adjust clock connections to improve connection to testbench	2021-11-30 00:16:47 -08:00
Alex Forencich	8f887005e5	Update Ethernet interface configuration detection in testbenches	2021-11-22 17:04:50 -08:00
Alex Forencich	2aa9158d5c	Limit scheduler pipeline to a single AXI lite operation	2021-11-19 16:29:16 -08:00
Alex Forencich	bc8a8cdc58	Update 100G designs to use correct clock for PTP RX timestamps	2021-11-19 01:54:58 -08:00
Alex Forencich	886111c9e6	Update 10G designs for PTP separate RX clock	2021-11-19 01:52:23 -08:00
Alex Forencich	74f4c6fc2d	Support using separate clock for PTP timestamps on RX path	2021-11-18 23:56:51 -08:00
Alex Forencich	af3b6312a9	Add PTP_USE_SAMPLE_CLOCK parameter to testbenches	2021-11-18 21:12:06 -08:00
Alex Forencich	c2d2b441fb	Add missing symlink	2021-11-17 18:29:26 -08:00
Alex Forencich	605965fec9	Add mqnic core logic module for AXI	2021-11-17 18:16:40 -08:00
Alex Forencich	5bf9de656c	Update testbenches	2021-11-17 18:08:40 -08:00
Alex Forencich	dc75f86980	merged changes in pcie	2021-11-17 17:38:57 -08:00
Alex Forencich	76e18d2af8	Add 10G mqnic design for Stratix 10 MX dev kit	2021-11-07 13:59:05 -08:00
Alex Forencich	bd8a0513ed	Add mqnic core logic for Stratix 10 GX/SX/TX/MX	2021-11-07 13:28:12 -08:00
Alex Forencich	7ab18f8602	Increase event FIFO depth	2021-11-06 16:14:49 -07:00
Alex Forencich	fb0f6f67f7	Remove debug code	2021-11-06 16:14:32 -07:00
Alex Forencich	f8a24d1c46	Add attributes to RAMs for proper synthesis in Quartus	2021-11-06 16:14:22 -07:00
Alex Forencich	cefb4568e7	merged changes in axi	2021-11-06 15:22:50 -07:00
Alex Forencich	aa89471cca	Add bus_num port to mqnic_core_pcie	2021-11-03 21:40:19 -07:00