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2,306 Commits 1 Branch 0 Tags
Commit Graph

501 Commits

Author SHA1 Message Date
Alex Forencich
e0cfb0c107 merged changes in pcie 2021-11-03 20:47:25 -07:00
Alex Forencich
ce6717cbee merged changes in eth 2021-11-03 20:47:21 -07:00
Alex Forencich
38c85a6bcd Set subsystem ID based on board, remove unnecessary configuration settings 2021-11-02 15:32:55 -07:00
Alex Forencich
dbd15cb60e Rework GT instances in VCU118 10G design 2021-10-21 22:16:05 -07:00
Alex Forencich
6e7109a3a0 Rework GT instances in VCU1525 10G design 2021-10-21 21:50:06 -07:00
Alex Forencich
b8eb3806a4 Rework GT instances in Alveo U280 10G design 2021-10-21 21:49:27 -07:00
Alex Forencich
bc7635e5dc Rework GT instances in Alveo U250 10G design 2021-10-21 21:48:49 -07:00
Alex Forencich
6a7a91856f Rework GT instances in Alveo U200 10G design 2021-10-21 19:58:22 -07:00
Alex Forencich
01871e46cb Rework GT instances in Alveo U50 10G design 2021-10-21 19:57:17 -07:00
Alex Forencich
6876ad4593 Rework GT instances in ZCU106 design 2021-10-21 19:00:47 -07:00
Alex Forencich
8f15664092 Rework GT instances in VCU118 design 2021-10-21 18:50:55 -07:00
Alex Forencich
cfe41e9680 Rework GT instances in ADM-PCIE-9V3 10G and 25G designs 2021-10-21 17:49:08 -07:00
Alex Forencich
2f5c15f513 Rework GT instances in fb2CG@KU15P 10G and 25G designs 2021-10-21 16:31:36 -07:00
Alex Forencich
d528949aa9 Rework GT instances in ExaNIC X10 design 2021-10-21 16:30:13 -07:00
Alex Forencich
5eca6389cf Rework GT instances in ExaNIC X25 10G and 25G designs 2021-10-21 16:29:48 -07:00
Alex Forencich
7ac4797336 Add default_nettype none and resetall directives 2021-10-20 21:53:39 -07:00
Alex Forencich
607257d7bb Fix connections 2021-10-20 20:43:11 -07:00
Alex Forencich
982edfeda7 Update file lists 2021-10-20 19:37:37 -07:00
Alex Forencich
dc0c5a17ff merged changes in pcie 2021-10-20 19:32:15 -07:00
Alex Forencich
87aca91fd9 merged changes in eth 2021-10-20 19:32:09 -07:00
Alex Forencich
e8359741f5 merged changes in axi 2021-10-20 19:32:04 -07:00
Alex Forencich
0a6665cada merged changes in eth 2021-10-17 22:55:09 -07:00
Alex Forencich
0dfd076f48 merged changes in eth 2021-10-13 18:22:19 -07:00
Alex Forencich
2c038c9b7b Update FIFO instance 2021-10-13 16:44:05 -07:00
Alex Forencich
74a7cc08e5 merged changes in eth 2021-10-13 16:41:04 -07:00
Alex Forencich
11f6522730 merged changes in pcie 2021-10-03 13:17:57 -07:00
Alex Forencich
780406197d Add 25G mqnic design for ExaNIC X25 2021-09-26 18:11:00 -07:00
Alex Forencich
92bb1bda57 Remove unused files 2021-09-26 18:00:36 -07:00
Alex Forencich
45b7e3566c Update readme 2021-09-26 01:16:34 -07:00
Alex Forencich
c8e6484af7 Use correct width for full throughput at 25G 2021-09-26 01:04:40 -07:00
Alex Forencich
39fbc194fd Update makefiles 2021-09-20 18:22:47 -07:00
Alex Forencich
1bee717bc8 Remove old TDMA variants 2021-09-13 17:20:44 -07:00
Alex Forencich
cc6348653d Add TDMA variants 2021-09-13 17:19:50 -07:00
Alex Forencich
620791e562 Add TDMA testbench 2021-09-13 17:11:39 -07:00
Alex Forencich
b1596751cf Update NetFPGA SUME design 2021-09-13 01:30:36 -07:00
Alex Forencich
f66f4d7cce Update VCU118 designs 2021-09-13 00:09:23 -07:00
Alex Forencich
bfea350194 Update VCU108 design 2021-09-12 23:17:50 -07:00
Alex Forencich
58a2dbd734 Update ZCU106 design 2021-09-12 23:17:01 -07:00
Alex Forencich
3f8becb186 Update ExaNIC X10 design 2021-09-12 21:56:33 -07:00
Alex Forencich
a18eced17f Update ExaNIC X25 design 2021-09-12 12:40:39 -07:00
Alex Forencich
49a2b6462f Update ADM-PCIE-9V3 designs 2021-09-11 23:22:08 -07:00
Alex Forencich
200ef77b09 Update VCU1525 designs 2021-09-11 20:07:32 -07:00
Alex Forencich
d7e9e91644 Fix FIFO size parameter defaults 2021-09-11 17:42:24 -07:00
Alex Forencich
26fdddb3ae Update Alveo U250 designs 2021-09-11 01:27:23 -07:00
Alex Forencich
ec89492d24 Fix control register addressing bug 2021-09-11 00:49:48 -07:00
Alex Forencich
ed418f101a Update Alveo U200 designs 2021-09-10 23:40:53 -07:00
Alex Forencich
9b1188860b Update Alveo U50 designs 2021-09-10 19:07:55 -07:00
Alex Forencich
079ad5ec37 Add pblock for 10G MACs 2021-09-10 18:52:46 -07:00
Alex Forencich
9ee5463b92 Remove blank line 2021-09-10 18:52:22 -07:00
Alex Forencich
6a44a59b2c Move LED assignments 2021-09-10 10:53:41 -07:00