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6 Commits

Author SHA1 Message Date
Alex Forencich
ae1f4a9a22 Rewrite early ready condition 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 19:25:30 -07:00
Alex Forencich
8cdb780ee3 Rewrite resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:57:26 -07:00
Alex Forencich
3a12483711 Fix multi-driven net issue when S_RAM_SEL_WIDTH = 0 2021-12-02 16:50:26 -08:00
Alex Forencich
d2c72d3583 Add attributes to RAMs for proper synthesis in Quartus 2021-11-02 22:28:05 -07:00
Alex Forencich
90959b8795 Add default_nettype none and resetall directives 2021-10-20 17:49:30 -07:00
Alex Forencich
292f73f43d Add DMA RAM demux modules 2021-08-16 18:03:38 -07:00