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Author SHA1 Message Date
Alex Forencich
64cdae1ccf fpga: Update designs for RX completion buffer management 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-31 10:26:40 -07:00
Alex Forencich
c45be17cea fpga/common: Add busy status outputs to DMA IF instances 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-30 21:27:56 -07:00
Alex Forencich
ffe158f43c merged changes in pcie 2023-05-30 21:27:16 -07:00
Alex Forencich
9cee4f3808 Update example designs for RX completion buffer management 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-30 18:38:43 -07:00
Alex Forencich
3d2feb36dc Add completion buffer management logic to DMA interface modu 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-30 18:37:44 -07:00
Alex Forencich
972ec36ce8 Add RCB status output to PCIe model 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-30 18:37:12 -07:00
Alex Forencich
b2de81fbd9 Add RCB status output to shims 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-30 14:26:32 -07:00
Alex Forencich
f59c5b78c8 Minor refactor of PCIe read request TLP size computation signals 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-28 01:02:24 -07:00
Alex Forencich
0828de78e8 Add DMA PSDPRAM master model and DMA PSDPRAM testbenches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-28 00:42:47 -07:00
Alex Forencich
cde909061c merged changes in eth 2023-05-21 14:53:37 -07:00
Alex Forencich
eb3343764d fpga/mqnic/DK_DEV_1SDX_P_A: Parameter clean-up 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-21 14:53:30 -07:00
Alex Forencich
47cfc828a2 fpga/mqnic/ADM_PCIE_9V3: Parameter clean-up, remove PCIE_TAG_COUNT from top level 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-19 13:34:33 -07:00
Alex Forencich
8ad370ac99 Properly handle PCIE_TAG_COUNT setting of 32 or less 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-17 19:12:09 -07:00
Alex Forencich
2f449d0b29 Rework write done handling in DMA ram demux module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-15 16:44:40 -07:00
Alex Forencich
4c82a8f465 Improve status FIFO utilization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-15 01:52:13 -07:00
Alex Forencich
b7dad0e946 fpga/common/tb: Check feature bits in core testbenches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-13 01:10:35 -07:00
Alex Forencich
1c242f7d92 fpga/common/tb: Pull out feature bits for easy access 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-13 00:54:56 -07:00
Alex Forencich
2d307a6d60 Add busy status outputs to DMA interface modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-12 16:05:44 -07:00
Alex Forencich
1a4692bf17 Increase flow control credit threshold for controlling the transmission of posted and non-posted requests in UltraScale shim 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-10 14:51:36 -07:00
Alex Forencich
6591849fe8 Generate wr_done output based only on wr_cmd_valid, not wr_cmd_be 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-10 14:46:47 -07:00
Alex Forencich
8b392d5127 Update to latest version of cocotbext-axi 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-06 22:37:41 -07:00
Alex Forencich
aef62af18c modules/mqnic: Associate messages with netdev 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-03 22:24:19 -07:00
Alex Forencich
335c731ef0 modules/mqnic: Implement ethtool reg dump API 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-03 17:44:14 -07:00
Alex Forencich
e76bc8128c modules/mqnic: Implement ethtool rxfh API 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-03 16:54:37 -07:00
Alex Forencich
32db67b066 modules/mqnic: Improve indirection table handling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-03 16:50:59 -07:00
Alex Forencich
eecaef6e6f modules/mqnic: Add some additional range enforcement 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-03 16:49:28 -07:00
Alex Forencich
7cd40a8e1e modules/mqnic: Minor cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-03 16:48:26 -07:00
Alex Forencich
eaceb0bfc7 modules/mqnic: More sensible default queue counts 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-03 01:38:23 -07:00
Alex Forencich
8faefe19cd modules/mqnic: Only allocate netdev queue resources for what is supported in HW 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-03 01:35:46 -07:00
Alex Forencich
a6da3a41cb modules/mqnic: Implement ethtool channels API 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-03 01:35:01 -07:00
Alex Forencich
3302c1f832 modules/mqnic: Implement ethtool ringparam API 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-03 01:22:12 -07:00
Alex Forencich
21b8d164cf modules/mqnic: Make mqnic_start_port/mqnic_stop_port non-static so they can be called from mqnic_ethtool 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-03 01:20:07 -07:00
Alex Forencich
3c995dc8e0 Implement dynamic queue allocation in testbench and driver 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-02 21:23:30 -07:00
Alex Forencich
d82f37b3b4 modules/mqnic: Rework teardown sequence 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-02 01:19:30 -07:00
Alex Forencich
9834f8365c Rework resource management in testbenches, driver, and utils 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-01 22:04:43 -07:00
Alex Forencich
1c7ae0ee73 modules/mqnic: Return pointers directly and use ERR_PTR during object creation 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-30 21:57:32 -07:00
Alex Forencich
66f5b9fcc1 Clean up naming in testbenches, driver, and utils 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-30 21:48:34 -07:00
Alex Forencich
01680f2ff5 modules/mqnic: Implement I2C interface for fb4CGg3@VU09P 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-30 13:57:29 -07:00
Alex Forencich
53d272ff12 fpga/mqnic/fb4CGg3: Add 25G mqnic design for Silicom fb4CGg3@VU09P 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-30 13:55:58 -07:00
Alex Forencich
341115d70b fpga/mqnic/fb4CGg3: Add 100G mqnic design for Silicom fb4CGg3@VU09P 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-30 13:51:57 -07:00
Alex Forencich
519330fd32 fpga: Move led_sreg_driver into common 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-27 14:12:42 -07:00
Alex Forencich
462d3c3a65 fpga/mqnic/fb2CG: Update led_sreg_driver to support interleaving and bit reversal 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-27 01:03:44 -07:00
Alex Forencich
d6a24d22ab docs: Update device lists 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-22 22:10:26 -07:00
Alex Forencich
04d137ffbc fpga/mqnic/DK_DEV_AGF014EA: Add notes on switch settings 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-22 22:10:02 -07:00
Alex Forencich
587b4d5743 fpga/mqnic/DK_DEV_1SDX_P_A: Add 100G mqnic design for DK-DEV-1SDX-P-A 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-22 22:07:32 -07:00
Alex Forencich
3d8bbc4b1c modules/mqnic: Add I2C code for Intel dev kits 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-22 21:58:56 -07:00
Alex Forencich
d1546c0f8e modules/mqnic: Update device IDs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-22 21:56:08 -07:00
Alex Forencich
0634b86539 fpga/mqnic/DK_DEV_1SDX_P_A: Implement I2C interface on DK-DEV-1SDX-P-A 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-22 20:24:50 -07:00
Alex Forencich
52068fbb31 fpga/mqnic: Rename Intel development kit designs based on part number 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-20 21:51:35 -07:00
Alex Forencich
56df4cb677 lib/mqnic: Add more JTAG IDs for Xilinx devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-16 23:14:23 -07:00