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Author SHA1 Message Date
Alex Forencich
65ead3a064 Update receive handling to allocate pages instead of skbs 2020-03-10 23:06:54 -07:00
Alex Forencich
8536b7d2b7 Minor refactor of CQ processing 2020-03-10 22:06:02 -07:00
Alex Forencich
37294142b8 Rework DMA mapping 2020-03-09 17:21:39 -07:00
Alex Forencich
1216f7a76e Offset packet start by 10 bytes to match Linux kernel skb alignment 2020-03-08 21:56:08 -07:00
Alex Forencich
23aef37aff Rewrite resets 2020-03-08 16:56:06 -07:00
Alex Forencich
24eae58e6c merged changes in pcie 2020-03-08 15:25:28 -07:00
Alex Forencich
248a0b4f93 Convert descriptor to DMA operation without storing in table 2020-03-08 00:22:55 -08:00
Alex Forencich
f7a1a7ef95 Add descriptor FIFOs 2020-03-07 22:28:59 -08:00
Alex Forencich
4dd5104f4d Stripe completion queues across event queues 2020-03-06 00:58:30 -08:00
Alex Forencich
627153cd9b Fix signal sizing bug 2020-03-06 00:24:13 -08:00
Alex Forencich
060320010d Don't configure MSI if already configured 2020-03-02 21:16:09 -08:00
Alex Forencich
37934485af Timing optimization for ram_wrap computation 2020-02-28 13:22:35 -08:00
Alex Forencich
983610d6d9 Timing optimization for mask computation 2020-02-28 13:02:26 -08:00
Alex Forencich
50124ce66d Timing optimization 2020-02-28 01:01:37 -08:00
Alex Forencich
db4d0a8f94 Timing optimizations 2020-02-27 20:00:37 -08:00
Alex Forencich
092c72ba66 Compute req_last_tlp in advance 2020-02-27 18:19:45 -08:00
Alex Forencich
18bf537f4f Fix register size 2020-02-27 15:47:18 -08:00
Alex Forencich
a00589e5a3 Timing optimizations 2020-02-27 15:24:24 -08:00
Alex Forencich
2b14ab2555 Update cmac_pad to pad frames to 60 bytes 2020-02-26 13:36:19 -08:00
Alex Forencich
7ebdceedf2 merged changes in pcie 2020-02-26 13:34:53 -08:00
Alex Forencich
bd0482fc96 Update script for sysfs changes 2020-02-26 12:21:36 -08:00
Alex Forencich
bfe537e614 Driver update for linux kernel API change 2020-02-25 12:36:43 -08:00
Alex Forencich
8d087ecc92 Consolidate example driver code 2020-02-13 13:16:05 -08:00
Alex Forencich
7977c3003b Support accessing card via sysfs without driver loaded 2020-02-03 17:05:21 -08:00
Alex Forencich
c3eba353fb Add checks for out-of-range pointers 2020-02-03 17:02:05 -08:00
Alex Forencich
fe8fdab002 Improve error handling 2020-02-03 17:01:00 -08:00
Alex Forencich
239b7ddd0b Add missing QSFP lpmode connections 2020-02-03 13:52:29 -08:00
Alex Forencich
63fcadaf0f Add missing refclk control connections 2020-01-30 12:22:44 -08:00
Alex Forencich
2f595be70e merged changes in pcie 2020-01-24 13:52:45 -08:00
Alex Forencich
ec2ceb8e56 Timing optimizations 2020-01-24 13:51:30 -08:00
Alex Forencich
4b25e6e9c9 Update readme 2020-01-17 10:27:56 -08:00
Alex Forencich
70450a4d89 Add 100G mqnic design for VCU1525 2020-01-16 23:36:32 -08:00
Alex Forencich
26b7b67b9b Add 10G mqnic design for VCU1525 2020-01-16 23:35:00 -08:00
Alex Forencich
73bb9a68c1 Add VCU1525 HW ID 2020-01-16 17:43:20 -08:00
Alex Forencich
3bad28d626 Add VCU1525 AXI example design 2020-01-15 22:43:33 -08:00
Alex Forencich
e7cadac773 Remove extraneous files 2019-12-31 22:35:25 -08:00
Alex Forencich
c9f36937ba Update readme 2019-12-31 22:02:10 -08:00
Alex Forencich
81842e3c50 Add 100G mqnic design for Alpha Data board 2019-12-31 21:43:39 -08:00
Alex Forencich
217217b45e Remove unused table fields 2019-12-30 22:02:22 -08:00
Alex Forencich
1a739b326d Dump PHC and TDMA registers 2019-12-30 21:03:00 -08:00
Alex Forencich
f6da532b97 Read PHC stride 2019-12-30 21:02:24 -08:00
Alex Forencich
8aeea9e110 Add perout offset and stride defines 2019-12-30 20:45:56 -08:00
Alex Forencich
f642bb7f7e Reserve packet data slot early and release on dequeue fail 2019-12-30 17:49:42 -08:00
Alex Forencich
91a538ff5f Change driver queue count limits 2019-12-29 23:40:07 -08:00
Alex Forencich
3737d85206 Use correct queue counts 2019-12-29 17:07:04 -08:00
Alex Forencich
a501f33c09 Update parameters 2019-12-29 16:46:25 -08:00
Alex Forencich
0955a4101f Fix signal widths 2019-12-29 16:45:32 -08:00
Alex Forencich
3690fdeb7d Pull out pipeline parameters 2019-12-28 01:16:16 -08:00
Alex Forencich
58200e9851 Fix testbench 2019-12-28 01:15:40 -08:00
Alex Forencich
db9e1df1fa Update pipelining to enable URAM inference 2019-12-28 01:13:57 -08:00