FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00
Code Issues Projects Releases Wiki Activity
82 Commits 1 Branch 0 Tags
Commit Graph

13 Commits

Author SHA1 Message Date
Alex Forencich
5a02ba2cb1 Use yield from more consistently 2018-10-23 21:24:39 -07:00
Alex Forencich
ab82ea5296 Match IP core ordering 2018-10-16 18:02:28 -07:00
Alex Forencich
6f9c2a1ed2 Add MSI support to Ultrascale PCIe model 2018-10-15 14:18:27 -07:00
Alex Forencich
35ccc2ffd5 Add pause signals 2018-10-15 14:17:00 -07:00
Alex Forencich
8ada97200f Update signal widths 2018-10-15 13:41:29 -07:00
Alex Forencich
76dccafe0e Consolidate MSI capability objects 2018-10-15 00:05:37 -07:00
Alex Forencich
c047716ae8 The only locked completions are for locked memory reads 2018-10-06 17:28:21 -07:00
Alex Forencich
2059e3b16f Generate is_eof_0 2018-10-06 17:27:16 -07:00
Alex Forencich
a2a43dd11d Fix parity polarity 2018-10-06 17:00:51 -07:00
Alex Forencich
2fef5c51df Add PcieId object 2018-10-01 15:41:00 -07:00
Alex Forencich
4eb0ab240d Add fmt_type property to TLP 2018-09-30 19:14:19 -07:00
Alex Forencich
16fdbba010 Fix RC packer bug 2018-09-28 01:06:36 -07:00
Alex Forencich
c57ef057ee Initial commit 2018-09-25 19:50:57 -07:00