316 Commits

Author	SHA1	Message	Date
Alex Forencich	6b85aed564	Any control characters in packet considered an error	2018-11-08 13:34:32 -08:00
Alex Forencich	ebe31e811c	Use parameters for control characters	2018-11-08 13:15:47 -08:00
Alex Forencich	6b1b36ded6	Assert header ready earlier if possible	2018-11-07 23:10:07 -08:00
Alex Forencich	b223c94adb	Use registered header	2018-11-07 23:08:40 -08:00
Alex Forencich	d2fedc4134	Rename ports	2018-11-07 22:35:06 -08:00
Alex Forencich	98fc042489	Convert generated udp_demux to verilog parametrized module	2018-11-02 00:39:52 -07:00
Alex Forencich	81e9aa0c77	Convert generated ip_demux to verilog parametrized module	2018-11-02 00:25:23 -07:00
Alex Forencich	18c4214edb	Convert generated eth_demux to verilog parametrized module	2018-11-02 00:23:31 -07:00
Alex Forencich	470ab887d9	Update mux instances	2018-11-01 00:59:14 -07:00
Alex Forencich	fea1186f57	Convert generated udp_arb_mux to verilog parametrized module	2018-11-01 00:48:26 -07:00
Alex Forencich	554e0a5380	Convert generated ip_arb_mux to verilog parametrized module	2018-11-01 00:40:09 -07:00
Alex Forencich	96cefbe0c1	Convert generated eth_arb_mux to verilog parametrized module	2018-10-31 21:42:28 -07:00
Alex Forencich	67025121ab	Convert generated udp_mux to verilog parametrized module	2018-10-31 18:09:44 -07:00
Alex Forencich	f20312b199	Convert generated ip_mux to verilog parametrized module	2018-10-31 18:08:39 -07:00
Alex Forencich	d28d459d70	Convert generated eth_mux to verilog parametrized module	2018-10-31 15:48:12 -07:00
Alex Forencich	ad8828d5b7	Update FIFO instances	2018-10-30 11:58:06 -07:00
Alex Forencich	fe0bf3b7c6	Remove old modules	2018-10-24 01:08:27 -07:00
Alex Forencich	0aca4c7dcc	Update 10G MAC to use new modules	2018-10-24 00:54:41 -07:00
Alex Forencich	de69975872	Add AXI stream XGMII RX and TX modules and testbenches	2018-10-23 23:34:43 -07:00
Alex Forencich	5e12f97518	MAC optimizations	2018-10-19 15:24:33 -07:00
Alex Forencich	5b7646ccda	Rework ARP subsystem	2018-06-18 13:59:58 -07:00
Alex Forencich	25d1b373cc	Use don't care bits	2018-06-14 15:20:20 -07:00
Alex Forencich	fea477db09	Add unused ports	2018-06-11 16:36:44 -07:00
Alex Forencich	3ae97c71a0	Add documentation	2018-06-04 18:21:55 -07:00
Alex Forencich	e95b39b36d	Update iddr/oddr Altera device support	2018-06-04 18:20:31 -07:00
Alex Forencich	6727e5a0bd	Happy new year	2018-02-27 01:47:56 -08:00
Alex Forencich	0fd157964a	Happy new year	2018-02-26 12:50:51 -08:00
Alex Forencich	bd27156f35	AXI stream updates	2018-02-26 00:08:08 -08:00
Alex Forencich	77211926f2	Fix classifier logic	2017-06-09 21:27:29 -07:00
Alex Forencich	9a507b388d	Update LFSR module	2017-06-09 21:17:28 -07:00
Alex Forencich	a3b5d5d167	Update RGMII PHY interface and add RGMII MAC wrappers	2017-05-31 18:40:49 -07:00
Alex Forencich	bb9e789645	Update GMII PHY interface and add GMII MAC wrappers	2017-05-31 18:40:18 -07:00
Alex Forencich	8ff4312601	Update MAC modules to use new modules	2017-05-31 18:37:33 -07:00
Alex Forencich	817e7c2667	Add AXI stream GMII RX and TX modules and testbenches	2017-05-31 16:11:20 -07:00
Alex Forencich	9b2ac9dfc1	Happy new year	2017-05-18 13:47:45 -07:00
Alex Forencich	270641b7a3	Update UDP modules and example designs to utilize UDP checksum modules	2016-09-30 22:15:21 -07:00
Alex Forencich	0b6614e8d4	Add UDP checksum generator modules and testbenches	2016-09-30 21:59:04 -07:00
Alex Forencich	15330486e8	Convert GMII and RGMII shims to use generic IO components	2016-09-29 20:10:10 -07:00
Alex Forencich	d13abd76c4	Add generic IO components	2016-09-29 20:07:29 -07:00
Alex Forencich	306c0ea590	Rework mux logic	2016-08-29 19:25:43 -07:00
Alex Forencich	a430e4463e	Add RGMII endpoint and PHY interface module	2016-06-29 06:13:46 -07:00
Alex Forencich	b38c643384	Add more implementation parameters to gmii_phy_if	2016-06-28 19:35:52 -07:00
Alex Forencich	635315c402	Remove generated eth_crc modules	2016-06-28 18:58:10 -07:00
Alex Forencich	47ca9a8725	Replace eth_crc modules for generic lfsr module	2016-06-28 17:31:58 -07:00
Alex Forencich	ccd8cd8c2e	Add generic LFSR module	2016-06-28 17:25:09 -07:00
Alex Forencich	3f2d096249	Add XGMII interleaver and deinterleaver	2016-01-25 00:50:51 -08:00
Alex Forencich	152486bebd	Update parametrization	2016-01-08 01:30:00 -08:00
Alex Forencich	9c01e114b4	Happy new year	2016-01-05 00:34:32 -08:00
Alex Forencich	a98dfce099	Update output registers, remove extraneous resets, fix constant widths	2015-11-09 23:50:34 -08:00
Alex Forencich	71235c0b92	64 bit Ethernet FCS checker optimizations	2015-11-03 15:32:23 -08:00