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Author SHA1 Message Date
Alex Forencich
67e0e07c43 fpga/mqnic/DK_DEV_AGF014EA: set port group size based on selected MAC rate 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-19 19:50:29 -08:00
Alex Forencich
c48735216c fpga/mqnic/Alveo: Rework AU200 clocking 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-19 19:50:07 -08:00
Alex Forencich
534cd3735f fpga/mqnic/Alveo: Rework AU55 clocking 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-15 11:28:35 -08:00
Alex Forencich
cccd983975 fpga/mqnic/Alveo: Rework AU280 clocking 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-15 11:28:14 -08:00
Alex Forencich
152c96dc00 fpga/mqnic/Alveo: Rework AU50 clocking 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-15 11:25:45 -08:00
Alex Forencich
0c35085714 fpga/common/rtl: Update scheduler block parameters and PTP connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-14 21:51:15 -08:00
Alex Forencich
614b33a205 fpga/mqnic/DK_DEV_1SDX_P_A: Fix MAC timing constraints for DK-DEV-1SDX-P-A 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-14 18:19:29 -08:00
Alex Forencich
55c5ea335f fpga/mqnic/DK_DEV_AGF014EA: Fix MAC timing constraints for DK-DEV-AGF014EA 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-14 18:13:25 -08:00
Alex Forencich
184b7242e9 fpga/mqnic/DE10_Agilex: Fix MAC timing constraints for DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-14 18:11:59 -08:00
Alex Forencich
545fb3ca22 fpga/mqnic/XUPP3R: Add missing TCL script for XUSP3S PCIe IP core 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-14 17:54:03 -08:00
Alex Forencich
3f7a4cee27 fpga/mqnic: Fix datapath width parameter for 25G 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 21:39:42 -08:00
Alex Forencich
09af3eb882 fpga/mqnic/DK_DEV_1SDX_P_A: Mege 25G into 100G for DK-DEV-1SDX-P-A 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 21:38:20 -08:00
Alex Forencich
cbb2dda130 fpga/mqnic/DK_DEV_AGF014EA: Merge 25G into 100G for DK-DEV-AGF014EA 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 21:22:20 -08:00
Alex Forencich
0002f0476a fpga/mqnic/DE10_Agilex: Merge 25G into 100G for DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 20:49:04 -08:00
Alex Forencich
3b70f93722 fpga/mqnic: Rework parametrization for Intel 100G designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 19:16:32 -08:00
Alex Forencich
12cb29f9ee Update device lists 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 16:43:53 -08:00
Alex Forencich
23a142b237 fpga/mqnic/Alveo: Minor cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 16:38:13 -08:00
Alex Forencich
2d1e322738 modules/mqnic: Add board ID for AU45 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 14:36:09 -08:00
Alex Forencich
1330e59233 lib/mqnic: Add XCU26 to FPGA ID list 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 14:35:40 -08:00
Alex Forencich
4f60691485 fpga/mqnic/Alveo: Add parameters for flash config 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 12:39:20 -08:00
Alex Forencich
b2f853cae7 Warn if the application BAR didn't get enumerated 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-12 19:15:40 -08:00
Alex Forencich
45a6250e43 Update FPGA ID list and adjust part matching to handle multiple parts with the same JTAG ID 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-12 19:09:56 -08:00
Alex Forencich
2cebcdfb2a Add support for Alveo U55N/Varium C1100 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-12 18:30:05 -08:00
Alex Forencich
1707142ab1 fpga/mqnic/Alveo: Fix HBM debug hub configuration 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-12 11:43:28 -08:00
Alex Forencich
dddc84d9fa fpga/mqnic: Merge AU50 into unified Alveo design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-12 00:56:56 -08:00
Alex Forencich
38a8a2588b fpga/mqnic: Merge AU280 into unified Alveo design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-11 23:57:56 -08:00
Alex Forencich
b8ef9cc92b fpga/mqnic/Alveo: Add HBM interfaces 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-11 16:34:17 -08:00
Alex Forencich
d3064877ea fpga/mqnic/Alveo: Rework Alveo parametrization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-11 13:39:33 -08:00
Alex Forencich
495c29f263 Update to latest cocotbext-eth 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-10 19:21:05 -08:00
Alex Forencich
7914445ac0 Rename AU200 to Alveo 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 22:48:37 -08:00
Alex Forencich
cd7ec5d5e3 fpga/mqnic Merge BittWare XUP-P3R and XUSP3S designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 22:27:54 -08:00
Alex Forencich
bd6ffeab99 fpga/mqnic: Merge Cisco Nexus K35-S and K3P-S designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 22:01:03 -08:00
Alex Forencich
2a7d0e0947 Use new PTP time distribution subsystem 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 21:57:07 -08:00
Alex Forencich
56887b8aed merged changes in eth 2023-11-07 13:50:38 -08:00
Alex Forencich
bd8e8e5b20 Add PTP time distribution components 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 13:07:15 -08:00
Alex Forencich
009560f583 Use latest version of cocotbext-eth 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 12:18:46 -08:00
Alex Forencich
01badce3a1 Remove unnecessary resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-01 18:30:32 -07:00
Alex Forencich
d78700d3bf fpga: Remove redundant RX PTP clock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-10-27 22:40:40 -07:00
Alex Forencich
6f2da7c1e9 fpga/common: Use async clocking for CMAC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-10-27 22:40:08 -07:00
Alex Forencich
18ac7cc4f4 fpga/mqnic: Merge AU200, AU250, and VCU1525 designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-10-12 23:26:08 -07:00
Alex Forencich
49513b45d4 Merge AU200, AU250, and VCU1525 designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-10-12 22:51:07 -07:00
Alex Forencich
858dc5ac85 fpga/common: Fix address space layout 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-10-12 22:34:09 -07:00
Alex Forencich
e84da8dbfb Update HTG-9200 readmes 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-26 23:12:52 -07:00
Alex Forencich
b5d1fadb7e Add makefiles for VU13P variant of HTG-9200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-26 15:07:16 -07:00
Alex Forencich
d9e4b82f7a fpga: PTP sample clock is no longer optional, so remove PTP_USE_SAMPLE_CLOCK parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-24 13:52:06 -07:00
Alex Forencich
66b1a28159 Update ptp_clock_cdc instances 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-24 13:48:27 -07:00
Alex Forencich
c9fc3473c1 merged changes in eth 2023-09-24 13:37:03 -07:00
Alex Forencich
994a2e9ef1 merged changes in pcie 2023-09-24 13:36:59 -07:00
Alex Forencich
5ff1e17a29 Add missing assign to frame_min_count_reg in axis_baser_tx_64 module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-24 13:35:29 -07:00
Alex Forencich
90e6dfc638 Use phase detector in PTP CDC module for coarse period tuning, use 9 LSBs of timestamp for fine sync to avoid rollover corrections, reduce FNS comparison width to 4 bits 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-23 14:58:44 -07:00