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Author SHA1 Message Date
Alex Forencich
adeb2c6b1c Fix alignment 2021-10-01 13:50:30 -07:00
Alex Forencich
d0705fea9b Minor optimizations to completion TLP size computation logic 2021-10-01 13:00:22 -07:00
Alex Forencich
a7b669e22f Update makefiles 2021-10-01 02:39:15 -07:00
Alex Forencich
c044898ec4 One AXI read burst per completion TLP 2021-10-01 00:20:29 -07:00
Alex Forencich
2984b5b09d Copy pcie_axil_master as pcie_axil_master_minimal 2021-09-30 22:38:28 -07:00
Alex Forencich
f2f19f7174 Update terminology, use byte_lanes instead of byte_width 2021-09-25 22:52:19 -07:00
Alex Forencich
bc8715decc Hold read completions until pending writes complete 2021-09-25 00:46:55 -07:00
Alex Forencich
f25cfa0982 Update tox configuration 2021-09-13 13:00:03 -07:00
Alex Forencich
b131b2ebbf Rework DMA desc status demux to fix X issue at t=0 2021-09-09 00:58:48 -07:00
Alex Forencich
f566df2c66 Add TLP mux and demux modules 2021-09-08 10:04:38 -07:00
Alex Forencich
1321e8e41a Refactor check 2021-09-05 15:30:37 -07:00
Alex Forencich
8a6abc51ed Add statistics outputs to DMA interface 2021-09-05 15:29:56 -07:00
Alex Forencich
6af4461705 Fix length register widths and max value handling 2021-08-20 16:09:58 -07:00
Alex Forencich
0563eb4727 Check MSBs 2021-08-20 14:12:26 -07:00
Alex Forencich
85391d2b9b Compare all fields 2021-08-20 14:10:03 -07:00
Alex Forencich
943731d624 Use new modules in dma_if_mux modules 2021-08-16 18:04:38 -07:00
Alex Forencich
292f73f43d Add DMA RAM demux modules 2021-08-16 18:03:38 -07:00
Alex Forencich
1342e31976 Add DMA IF descriptor mux module 2021-08-16 18:03:22 -07:00
Alex Forencich
14c84088ee Reorganize driver code 2021-08-13 14:22:32 -07:00
Alex Forencich
7810b3c99e Connect RQ sequence number ports in pcie_us_if testbench 2021-08-11 19:53:28 -07:00
Alex Forencich
7fed6876a3 Init seq to 0 2021-08-11 19:52:47 -07:00
Alex Forencich
ac96ae97d3 Add flow control signals to pcie_us_if 2021-08-11 19:37:51 -07:00
Alex Forencich
811b9daa63 Add missing connection 2021-08-11 19:18:50 -07:00
Alex Forencich
8e19f6edb8 Tie off outputs if configuration read functionality is disabled 2021-08-11 19:17:55 -07:00
Alex Forencich
c47f3f5280 AT is reserved in completions 2021-08-06 01:49:47 -07:00
Alex Forencich
1c424a8a51 Read locked is UR for PCIe endpoints 2021-08-06 01:39:11 -07:00
Alex Forencich
f8f95a214b Set completer ID in testbench 2021-08-04 17:08:25 -07:00
Alex Forencich
d3690a12ab Update readme 2021-08-04 01:04:31 -07:00
Alex Forencich
12f90eac5b Update test durations 2021-08-04 01:04:20 -07:00
Alex Forencich
836d14bad6 Add PCIe interface shim for Xilinx UltraScale 2021-08-04 01:03:31 -07:00
Alex Forencich
b95f030408 Add PCIe DMA interface modules and testbenches 2021-08-04 01:02:48 -07:00
Alex Forencich
1a5e96d0fd Add PCIe AXI lite master module and testbench 2021-08-04 01:01:22 -07:00
Alex Forencich
623cc1ae8d Add generic PCIe interface model 2021-08-03 22:33:23 -07:00
Alex Forencich
e4508b242f Update example designs 2021-08-02 18:36:25 -07:00
Alex Forencich
36ec7aaa16 Add error reporting to DMA modules 2021-08-02 17:24:00 -07:00
Alex Forencich
dad637bd00 Properly handle zero-length DMA operations 2021-07-25 01:36:40 -07:00
Alex Forencich
59c026b1b8 Fix parameters 2021-07-24 02:02:30 -07:00
Alex Forencich
3e03b20bc7 Properly handle zero-length PCIe read and write operations 2021-07-24 01:13:25 -07:00
Alex Forencich
c7a59c5f15 Split read requests on RCB 2021-06-27 01:31:40 -07:00
Alex Forencich
36a361d7c3 Update test durations 2021-06-18 18:42:44 -07:00
Alex Forencich
6b0076debc Work around pytest-split bug 2021-06-18 18:41:26 -07:00
Alex Forencich
ccc44d7dbb Use 64 bit BARs in example designs 2021-06-16 23:23:53 -07:00
Alex Forencich
a79027fdd1 Remove DEV_BAR_CNT define 2021-06-16 21:36:34 -07:00
Alex Forencich
31378c4e85 Remove string parameters 2021-06-02 17:05:29 -07:00
Alex Forencich
e4e05ed1e3 Update readme 2021-06-01 16:29:52 -07:00
Alex Forencich
0d21ea80ea Update readme 2021-05-18 22:16:50 -07:00
Alex Forencich
1a046d8e82 Update testbenches 2021-04-15 23:30:14 -07:00
Alex Forencich
77ff92f02b Avoid sampling own outputs 2021-04-05 20:38:05 -07:00
Alex Forencich
5f90e39e59 Use correct assignment type 2021-03-30 21:53:01 -07:00
Alex Forencich
4adee5db8f Use release version of cocotb for CI 2021-03-17 22:54:46 -07:00