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12 Commits

Author SHA1 Message Date
Alex Forencich
9b2ac9dfc1 Happy new year 2017-05-18 13:47:45 -07:00
Alex Forencich
306c0ea590 Rework mux logic 2016-08-29 19:25:43 -07:00
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
a98dfce099 Update output registers, remove extraneous resets, fix constant widths 2015-11-09 23:50:34 -08:00
Alex Forencich
2a59c7db1c Update generate scripts to use argparse 2015-10-19 19:26:59 -07:00
Alex Forencich
cc5fead04d Convert to synchronous resets 2015-10-09 22:36:58 -07:00
Alex Forencich
af8bed8237 Update for compatibility with older versions of Python 2015-07-14 08:29:54 -07:00
Alex Forencich
2667c9c631 Update for compatibility with older version of Python 2015-07-09 11:35:55 -07:00
Alex Forencich
885d847514 Rework header ready set 2014-11-17 19:27:45 -08:00
Alex Forencich
59952bd8cf Do not accept new frame until header is read 2014-11-17 18:10:35 -08:00
Alex Forencich
f1d075d974 Add enable signal 2014-11-16 02:13:43 -08:00
Alex Forencich
9bee01e74c Add ethernet mux and testbench 2014-11-14 17:48:51 -08:00