131 Commits

Author	SHA1	Message	Date
Alex Forencich	1f76606667	Move TDMA registers	2020-05-01 16:55:57 -07:00
Alex Forencich	9e64d19ea5	Use scatter descriptor blocks in driver model	2020-04-21 01:04:07 -07:00
Alex Forencich	2c6e9673f7	Add log_desc_block_size ring parameter in driver model	2020-04-21 00:58:12 -07:00
Alex Forencich	d0cf549057	Add log desc block size field to queue manager	2020-04-20 20:45:10 -07:00
Alex Forencich	50af74aa88	Change QUEUE_LOG_SIZE_WIDTH to LOG_QUEUE_SIZE_WIDTH	2020-04-20 18:43:26 -07:00
Alex Forencich	a196cd227c	Enable bus mastering and MSI in driver model	2020-03-12 15:32:08 -07:00
Alex Forencich	457f4d7f3f	Use configured ring stride	2020-03-12 15:28:00 -07:00
Alex Forencich	0c32192226	Use constants instead of magic numbers	2020-03-12 15:08:20 -07:00
Alex Forencich	1216f7a76e	Offset packet start by 10 bytes to match Linux kernel skb alignment	2020-03-08 21:56:08 -07:00
Alex Forencich	4dd5104f4d	Stripe completion queues across event queues	2020-03-06 00:58:30 -08:00
Alex Forencich	58200e9851	Fix testbench	2019-12-28 01:15:40 -08:00
Alex Forencich	f97ff4407b	Change driver model max packet size	2019-12-23 14:41:52 -08:00
Alex Forencich	b5d7bd15b4	Add rx_hash module and testbenches	2019-12-05 13:47:07 -08:00
Alex Forencich	463f2053b0	Add port register port_mtu	2019-11-18 16:30:32 -08:00
Alex Forencich	489506e4c0	Add FPGA ID register	2019-11-17 12:46:27 -08:00
Alex Forencich	bce2756c0c	Parametrize checksum offload	2019-11-13 23:49:50 -08:00
Alex Forencich	f53a6b20e8	Add timeslot count to port registers	2019-11-05 16:59:40 -08:00
Alex Forencich	e92485a41e	Fix register definitions	2019-11-05 16:44:57 -08:00
Alex Forencich	6d78315f81	Add queue index to queue operation response	2019-09-01 08:12:06 -07:00
Alex Forencich	a4132cfda7	Integrate TX checksum offload	2019-08-22 00:45:09 -07:00
Alex Forencich	3b6bca6b93	Add transmit checksum module and testbench	2019-08-21 22:57:41 -07:00
Alex Forencich	7b2a0d5032	Sync driver model	2019-08-20 01:36:22 -07:00
Alex Forencich	d99f40db08	Add port CSRs	2019-08-13 00:27:09 -07:00
Alex Forencich	1e06d7cca7	Clean up pipeline parameters	2019-08-11 09:55:10 -07:00
Alex Forencich	4c3f2412df	Add TDMA BERT modules and testbenches	2019-07-19 15:28:57 -07:00
Alex Forencich	fcd8b1b8e9	Add driver simulation model	2019-07-17 16:46:12 -07:00
Alex Forencich	6100e3ad78	Add RX checksum module and testbench	2019-07-16 00:42:49 -07:00
Alex Forencich	a653f2d839	Add TDMA scheduler module and testbench	2019-07-16 00:19:22 -07:00
Alex Forencich	fc9a6c1c50	Add completion queue manager module and testbench	2019-07-16 00:16:07 -07:00
Alex Forencich	46f653f097	Add queue manager module and testbench	2019-07-16 00:15:50 -07:00
Alex Forencich	3d4ba0fa3f	Add testbench symlinks	2019-07-16 00:15:25 -07:00