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3 Commits

Author SHA1 Message Date
Alex Forencich
6af4461705 Fix length register widths and max value handling 2021-08-20 16:09:58 -07:00
Alex Forencich
0563eb4727 Check MSBs 2021-08-20 14:12:26 -07:00
Alex Forencich
b95f030408 Add PCIe DMA interface modules and testbenches 2021-08-04 01:02:48 -07:00