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Author SHA1 Message Date
Alex Forencich
7b713199ad Add AXI nonblocking crossbar interconnect module and testbench 2019-02-25 18:37:46 -08:00
Alex Forencich
365e063bc7 Add AXI DMA and CDMA descriptor mux modules 2019-02-25 15:44:10 -08:00
Alex Forencich
04dd6a34d7 Fix combinatorial loop 2019-02-20 18:48:27 -08:00
Alex Forencich
6baede4717 Broadcast message support 2019-02-15 18:04:46 -08:00
Alex Forencich
1630200cd8 Implement proper downstream TLP routing 2019-02-15 17:55:24 -08:00
Alex Forencich
178133498b Fix indentation 2019-02-15 17:23:33 -08:00
Alex Forencich
13d35569fa Match IO bars for routing IO operations 2019-02-15 17:23:14 -08:00
Alex Forencich
35a4d62fb8 Split SwitchBridge into separate upstream and downstream ports 2019-02-15 16:56:21 -08:00
Alex Forencich
247bca01f3 Add default_switch_port parameter 2019-02-15 15:26:09 -08:00
Alex Forencich
8cb607be04 Fix calls to read and write root complex regions 2019-02-15 14:40:24 -08:00
Alex Forencich
7654d874ae Fix out of range access due to off by one error 2019-02-11 19:30:57 -08:00
Alex Forencich
cd6b87e984 Enable bitstream compression in example designs 2019-02-06 21:25:30 -08:00
Alex Forencich
52058cb5de Swap out PHY in VCU118 example design 2019-02-05 18:28:42 -08:00
Alex Forencich
57dd292ae9 Add AXI RAM interface modules, AXI dual port RAM module, and testbench 2019-02-01 18:22:03 -08:00
Alex Forencich
199a5544ca Use correct wait 2019-02-01 17:28:22 -08:00
Alex Forencich
22b3d05954 Update readme 2019-01-31 18:20:31 -08:00
Alex Forencich
c1fe89db62 Add bit reverse support to serdes endpoint 2019-01-31 18:14:06 -08:00
Alex Forencich
ec38440d89 Add 10G Ethernet MAC/PHY combination modules and testbenches 2019-01-31 18:13:07 -08:00
Alex Forencich
5f6e7f721c Update testbench 2019-01-31 18:12:07 -08:00
Alex Forencich
e644ce3895 Add start packet strobe timing outputs to MAC modules 2019-01-31 17:00:23 -08:00
Alex Forencich
9f36acebc2 Print TLP payloads in hex 2019-01-28 18:17:21 -08:00
Alex Forencich
667b5c42c5 Add support for registering MSI callbacks 2019-01-28 16:30:19 -08:00
Alex Forencich
201c5faa80 Always ready on RC channel in idle for 64 bits 2019-01-22 23:00:17 -08:00
Alex Forencich
4422b908bf Backpressure for awvalid 2019-01-22 22:54:40 -08:00
Alex Forencich
fac972bfe6 RC channel backpressure fix 2019-01-22 22:50:15 -08:00
Alex Forencich
263bb5c670 Index based on correct tag value 2019-01-22 22:47:15 -08:00
Alex Forencich
a743f6f789 Add zero IFG forced offset start test 2019-01-22 18:47:32 -08:00
Alex Forencich
5b2d4fd465 Add force offset start parameter 2019-01-22 18:46:34 -08:00
Alex Forencich
4d2090a1a5 Fix off-by-one error in control character checks 2019-01-22 14:24:35 -08:00
Alex Forencich
92df3778ea Fix DIC implementation in testbench 2019-01-22 14:23:29 -08:00
Alex Forencich
9ae60dcd9a Simplify lane swapping code 2019-01-22 14:22:01 -08:00
Alex Forencich
54e31c51b7 Adjustment to scrambler bypass 2019-01-22 14:21:14 -08:00
Alex Forencich
6238ed5755 Report error for invalid encoding 2019-01-22 14:19:43 -08:00
Alex Forencich
e784900050 Remove unused code 2019-01-22 14:18:27 -08:00
Alex Forencich
a060d2eed9 Update readme 2019-01-18 16:22:24 -08:00
Alex Forencich
07b4efa9ba Switch out Xilinx PHY core in ExaNIC X10 example design 2019-01-18 13:49:46 -08:00
Alex Forencich
0bbe062c66 Switch out Xilinx PHY core in ADM-PCIE-9V3 example design 2019-01-18 13:32:58 -08:00
Alex Forencich
2e29aea857 Fix input clock period settings 2019-01-17 19:09:47 -08:00
Alex Forencich
787f198970 Add AXI lite dual-port RAM module and testbench 2019-01-17 17:48:23 -08:00
Alex Forencich
b1f40411ad Remove unnecessary reset 2019-01-17 17:09:55 -08:00
Alex Forencich
818fac5daa Update signal names 2019-01-16 19:37:15 -08:00
Alex Forencich
dbbbc28059 Add 10G Ethernet PHY modules and testbenches 2019-01-16 18:00:56 -08:00
Alex Forencich
91553e6edf Add XGMII 10GBASE-R encoder and decoder modules and testbenches 2019-01-16 17:30:07 -08:00
Alex Forencich
c9752f24dd Add BASE-R SERDES endpoint model 2019-01-16 17:26:19 -08:00
Alex Forencich
5fbd67501c Clamp ifg_cnt at zero 2019-01-16 17:25:08 -08:00
Alex Forencich
128dc292a1 Add short IFG tests 2019-01-16 13:27:28 -08:00
Alex Forencich
ea02b6c898 Properly handle short IFG 2019-01-16 13:26:47 -08:00
Alex Forencich
32d889b20d Remove unreachable code 2019-01-16 13:26:14 -08:00
Alex Forencich
bf94ef56b8 Move ifg parameter 2019-01-16 13:23:02 -08:00
Alex Forencich
b8b504682a Fix transceiver clocking 2019-01-15 00:30:36 -08:00